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1. 发明授权

US09647623B2 Signal processor suitable for low intermediate frequency (LIF) or zero intermediate frequency (ZIF) operation 有权
公开(公告)号：US09647623B2
公开(公告)日：2017-05-09
申请号：US12571092
申请日：2009-09-30
申请人： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin Khoini-Poorfard , James T. Kao
发明人： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin Khoini-Poorfard , James T. Kao
IPC分类号： H04B1/06 , H03G3/30
CPC分类号： H04B1/16 , H03G3/3068
摘要： A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.

2. 发明申请

US20110076977A1 Signal Processor Suitable for Low Intermediate Frequency (LIF) or Zero Intermediate Frequency (ZIF) Operation 有权
标题翻译：信号处理器适用于低中频（LIF）或零中频（ZIF）操作
公开(公告)号：US20110076977A1
公开(公告)日：2011-03-31
申请号：US12571092
申请日：2009-09-30
申请人： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin Khoini-Poorfard , James T. Kao
发明人： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin Khoini-Poorfard , James T. Kao
IPC分类号： H04B1/06
CPC分类号： H04B1/16 , H03G3/3068
摘要： A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.
摘要翻译：一种用于射频（RF）接收机的信号处理器包括多个分布式信号处理元件，其中第一个接收输入信号，最后一个提供输出信号，并且多个增益元素散布在所述多个的分布式信号处理元件。信号处理器还包括耦合到所述多个增益元件中对应的增益元件的相应输出端的相同的多个峰值检测器，以及具有耦合到每个峰值检测器的输出的输入的自动增益控制器，以及耦合到多个获得元素。自动增益控制器独立地控制多个增益元件中的每一个以形成相同的多个独立的自动增益控制（AGC）回路。

3. 发明授权

US06448840B2 Adaptive body biasing circuit and method 失效
标题翻译：自适应体偏置电路及方法
公开(公告)号：US06448840B2
公开(公告)日：2002-09-10
申请号：US09452080
申请日：1999-11-30
申请人： James T. Kao , Vivek K. De , Siva G. Narendra , Rajendran Nair
发明人： James T. Kao , Vivek K. De , Siva G. Narendra , Rajendran Nair
IPC分类号： H03K301
CPC分类号： H01L27/0222 , H03K17/145 , H03K2217/0018
摘要： An adaptive body bias circuit forward or reverse biases bodies of transistors within a compensated circuit as a result of measured parameters of an integrated circuit. The adaptive body bias circuit includes a matched circuit that includes a replica of a signal path within the compensated circuit. The phase of a clock signal at the input to the matched circuit is compared to a phase of a delayed clock signal at the output of the matched circuit. When the delay through the matched circuit varies about one period of the clock signal, a non-zero error value is produced. A bias voltage is generated as a function of the error value, and the bias voltage is applied to the compensated circuit as well as the matched circuit. Integrated circuits can include many adaptive body bias circuits. Bias values can be stored in memories for later use, and bias values within memories can be updated periodically to compensate the circuit over time.
摘要翻译：作为集成电路的测量参数的结果，自适应体偏置电路正向或反向偏置补偿电路内的晶体管本体。自适应体偏置电路包括匹配电路，其包括补偿电路内的信号路径的副本。将匹配电路的输入端的时钟信号的相位与匹配电路输出端的延迟时钟信号的相位进行比较。当通过匹配电路的延迟在时钟信号的一个周期上变化时，产生非零误差值。产生偏置电压作为误差值的函数，并且偏置电压被施加到补偿电路以及匹配电路。集成电路可以包括许多自适应体偏置电路。偏置值可以存储在存储器中以供以后使用，并且周期性地更新存储器内的偏置值以补偿电路随时间变化。

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