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1. 发明申请

US20130134518A1 NOBLE GAS IMPLANTATION REGION IN TOP SILICON LAYER OF SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
标题翻译：半导体绝缘体基板的顶层硅层中的气体植入区域
公开(公告)号：US20130134518A1
公开(公告)日：2013-05-30
申请号：US13280681
申请日：2011-11-28
申请人： Alan B. Botula , William F. Clark, JR. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , William F. Clark, JR. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L21/84 , H01L27/1203
摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.
摘要翻译：半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。

2. 发明授权

US08748285B2 Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate 有权
标题翻译：绝缘体上半导体衬底顶硅层中的高气体注入区
公开(公告)号：US08748285B2
公开(公告)日：2014-06-10
申请号：US13280681
申请日：2011-11-28
申请人： Alan B. Botula , William F. Clark, Jr. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , William F. Clark, Jr. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
IPC分类号： H01L21/76
CPC分类号： H01L21/84 , H01L27/1203
摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.
摘要翻译：半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。

3. 发明申请

US20110127529A1 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：用于减少谐波的硅绝缘体（SOI）结构和形成结构的方法
公开(公告)号：US20110127529A1
公开(公告)日：2011-06-02
申请号：US12627343
申请日：2009-11-30
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/02488 , H01L21/2652 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于形成这种半导体结构的方法的实施例。

4. 发明授权

US08698244B2 Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method 有权
标题翻译：绝缘体上硅（SOI）结构配置为减少谐波，设计结构和方法
公开(公告)号：US08698244B2
公开(公告)日：2014-04-15
申请号：US12634893
申请日：2009-12-10
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于这种半导体结构的方法和设计结构的实施例。

5. 发明授权

US08471340B2 Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure 有权
公开(公告)号：US08471340B2
公开(公告)日：2013-06-25
申请号：US12627343
申请日：2009-11-30
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L21/70
CPC分类号： H01L21/02488 , H01L21/2652 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

6. 发明申请

US20110131542A1 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 有权
标题翻译：用于减少谐波的硅绝缘体（SOI）结构，设计结构和方法
公开(公告)号：US20110131542A1
公开(公告)日：2011-06-02
申请号：US12634893
申请日：2009-12-10
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： G06F17/50
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于这种半导体结构的方法和设计结构的实施例。

7. 发明授权

US08916467B2 SOI radio frequency switch with enhanced signal fidelity and electrical isolation 有权
标题翻译：具有增强的信号保真度和电隔离的SOI射频开关
公开(公告)号：US08916467B2
公开(公告)日：2014-12-23
申请号：US13116396
申请日：2011-05-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H03K3/01 , H01L21/336 , G06F17/50 , H01L21/762 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

8. 发明授权

US08133774B2 SOI radio frequency switch with enhanced electrical isolation 有权
标题翻译： SOI射频开关具有增强的电气隔离
公开(公告)号：US08133774B2
公开(公告)日：2012-03-13
申请号：US12411494
申请日：2009-03-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译：至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

9. 发明授权

US07999320B2 SOI radio frequency switch with enhanced signal fidelity and electrical isolation 有权
标题翻译：具有增强的信号保真度和电隔离的SOI射频开关
公开(公告)号：US07999320B2
公开(公告)日：2011-08-16
申请号：US12342527
申请日：2008-12-23
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L27/01 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

10. 发明授权

US08866226B2 SOI radio frequency switch with enhanced electrical isolation 有权
标题翻译： SOI射频开关具有增强的电气隔离
公开(公告)号：US08866226B2
公开(公告)日：2014-10-21
申请号：US13345871
申请日：2012-01-09
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L27/12 , H01L21/84 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译：至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

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