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1. 发明授权

US06744080B2 Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor 有权
标题翻译：制造双晶硅，异质结基极型和相应晶体管的双极晶体管的方法
公开(公告)号：US06744080B2
公开(公告)日：2004-06-01
申请号：US10097651
申请日：2002-03-13
申请人： Alain Chantre , Helene Baudry , Didier Dutartre
发明人： Alain Chantre , Helene Baudry , Didier Dutartre
IPC分类号： H01L2973
CPC分类号： H01L29/66242 , H01L29/7378
摘要： Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.
摘要翻译：晶体管和双晶硅异质结基极型双极晶体管的制造方法，其中具有SiGe异质结的半导体层通过非选择性外延在衬底的有源区和围绕有源区的绝缘区形成。在有源区域的一部分上方的半导体层上形成至少一个阻挡层。在半导体层和停止层的一部分上形成多晶硅层和上绝缘层，留下发射器窗口。发射极区域通过在发射极窗中外延形成，部分地搁置在上绝缘层上并与半导体层接触。

2. 发明授权

US06551891B1 Process for fabricating a self-aligned vertical bipolar transistor 有权
标题翻译：制造自对准垂直双极晶体管的工艺
公开(公告)号：US06551891B1
公开(公告)日：2003-04-22
申请号：US09668428
申请日：2000-09-22
申请人： Alain Chantre , Michel Marty , Helene Baudry
发明人： Alain Chantre , Michel Marty , Helene Baudry
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/66272
摘要： The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window, so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.
摘要翻译：该制造工艺包括产生具有非本征基极和本征基极的基极区域的相位，以及产生发射极区域的相位，该发射极区域包括位于位于本征基底之上的发射极窗口中的较窄的下部的发射极阵列。外部基极的制造包括在发射极窗口被限定之后进行的掺杂剂的注入，并且在距离发射器窗口的横向边界的预定距离dp处，以便相对于该自对准发射极窗口，并且在发射极块形成之前。

3. 发明授权

US06642096B2 Bipolar transistor manufacturing 有权
公开(公告)号：US06642096B2
公开(公告)日：2003-11-04
申请号：US09947190
申请日：2001-09-05
申请人： Didier Dutartre , Alain Chantre , Michel Marty , Sébastien Jouan
发明人： Didier Dutartre , Alain Chantre , Michel Marty , Sébastien Jouan
IPC分类号： H01L218249
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/66272
摘要： A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

4. 发明授权

US06472262B2 Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor 有权
标题翻译：用于制造具有异质结基极和相应晶体管的自对准双多晶硅型双极晶体管的方法
公开(公告)号：US06472262B2
公开(公告)日：2002-10-29
申请号：US09817898
申请日：2001-03-26
申请人： Alain Chantre , Didier Dutartre , Hélène Baudry
发明人： Alain Chantre , Didier Dutartre , Hélène Baudry
IPC分类号： H01L218249
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.
摘要翻译：具有异质结基底的自对准双多晶硅型双极晶体管包括位于半导体衬底的有源区上方的半导体异质结区域和界定有源区域的隔离区域，以及掺入晶体管的本征基极区域。位于有源区上方并与半导体异质结区的上表面接触的发射极区。形成晶体管的非本征基极区域的多晶硅层，位于发射极区域的每一侧，并且通过分离层与半导体异质结区域分离，所述分离层包括位于发射极区域正前方的导电连接部分。该连接部件确保外部基座和内部基座之间的电接触。

5. 发明授权

US06656812B1 Vertical bipolar transistor having little low-frequency noise and high current gain, and corresponding fabrication process 有权
标题翻译：具有低频噪声和高电流增益的垂直双极晶体管，以及相应的制造工艺
公开(公告)号：US06656812B1
公开(公告)日：2003-12-02
申请号：US09717825
申请日：2000-11-21
申请人： Michel Marty , Didier Dutartre , Alain Chantre , Sébastien Jouan , Pierre Llinares
发明人： Michel Marty , Didier Dutartre , Alain Chantre , Sébastien Jouan , Pierre Llinares
IPC分类号： H01L21331
CPC分类号： H01L29/0895
摘要： A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.
摘要翻译：垂直双极晶体管包括半导体衬底，半导体衬底中的非本征集电极层，非本征集电极上的本征集电极，围绕本征集电极的上部的横向隔离区，偏移的外在集电极阱，包括半导体在包含至少一个硅层的横向隔离区域上方以及由该基极包围的掺杂发射极之上。掺杂发射器可以包括第一和第二部分。第一部分可以由单晶硅形成，并且在本征收集器上方的上表面中的预定窗口中与半导体区域的上表面直接接触。第二部分可以由多晶硅形成。发射极的两个部分可以通过与晶体管的发射极 - 基极结间隔开的分离氧化物层来分离。

6. 发明授权

US06177717B1 Low-noise vertical bipolar transistor and corresponding fabrication process 有权
标题翻译：低噪声垂直双极晶体管及相应的制造工艺
公开(公告)号：US06177717B1
公开(公告)日：2001-01-23
申请号：US09323418
申请日：1999-06-01
申请人： Alain Chantre , Michel Marty , Didier Dutartre , Augustin Monroy , Michel Laurens , Francois Guette
发明人： Alain Chantre , Michel Marty , Didier Dutartre , Augustin Monroy , Michel Laurens , Francois Guette
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L29/0826 , H01L29/7378
摘要： The intrinsic collector of a vertical bipolar transitor is grown epitaxially on an extrinsic collector layer buried in a semiconductor substrate. A lateral isolation region surrounds the upper part of the intrinsic collector and an offset extrinsic collector well is produced. An SiGe heterojunction base lying above the intrinsic collector and above the lateral isolation region is produced by non-selective epitaxy. An in-situ doped emitter is produced by epitaxy on a predetermined window in the surface of the base which lies above the intrinsic collector so as to obtain, at least above the window, an emitter region formed from single-crystal silicon and directly in contact with the silicon of the base.
摘要翻译：垂直双极性偏转器的本征集电极外延生长在埋在半导体衬底中的非本征集电极层上。横向隔离区域围绕本征收集器的上部，并产生偏移的外部收集阱。通过非选择性外延生产位于本征收集器之上和横向隔离区上方的SiGe异质结基底。原位掺杂的发射体通过在位于本征集电极上方的基底表面上的预定窗口上外延生长，以便至少在窗口上方获得由单晶硅形成并直接接触的发射极区域与基底的硅。

7. 发明申请

US20050037587A1 Heterojunction bipolar transistor 审中-公开
标题翻译：异质结双极晶体管
公开(公告)号：US20050037587A1
公开(公告)日：2005-02-17
申请号：US10914482
申请日：2004-08-09
申请人： Bertrand Martinet , Michel Marty , Pascal Chevalier , Alain Chantre
发明人： Bertrand Martinet , Michel Marty , Pascal Chevalier , Alain Chantre
IPC分类号： H01L21/331 , H01L29/08 , H01L21/8222
CPC分类号： H01L29/66287 , H01L29/0817 , H01L29/66242
摘要： A method for forming a heterojunction bipolar transistor including the steps of: forming in a semiconductor substrate a collector area of a first doping type; growing by epitaxy above a portion of the collector area a silicon/germanium layer of a second doping type forming a base area; forming above the silicon/germanium layer a sacrificial emitter formed of a material selectively etchable with respect to the silicon/germanium layer and with respect to the layers and consecutively-formed insulating spacers; forming first insulating spacers on the sides of the sacrificial emitter; growing by epitaxy a silicon layer above the exposed portions of the silicon/germanium layer; forming second insulating spacers adjacent to the first spacers and laid on the silicon layer; covering the entire structure with an insulating layer; partially removing the insulating layer above the sacrificial emitter and removing the sacrificial emitter; filling the space previously taken up by the sacrificial emitter with a semiconductor material of the first doping type.
摘要翻译：一种用于形成异质结双极晶体管的方法，包括以下步骤：在半导体衬底中形成第一掺杂类型的集电极区域; 通过在集电区域的一部分上方的外延生长形成基区的第二掺杂类型的硅/锗层; 在硅/锗层之上形成由相对于硅/锗层可选择性地蚀刻的材料以及相对于层和连续形成的绝缘间隔物形成的牺牲发射体; 在所述牺牲发射体的侧面上形成第一绝缘间隔物; 通过将硅/锗层的暴露部分上的硅层外延生长; 形成与所述第一间隔物相邻的第二绝缘间隔物并铺设在所述硅层上; 用绝缘层覆盖整个结构; 部分去除牺牲发射体上方的绝缘层并去除牺牲发射极; 用第一掺杂类型的半导体材料填充先前由牺牲发射极占据的空间。

8. 发明授权

US06403437B1 Method for making hyperfrequency transistor 失效
标题翻译：制造超频晶体管的方法
公开(公告)号：US06403437B1
公开(公告)日：2002-06-11
申请号：US09445425
申请日：1999-12-29
申请人： Alain Chantre , Jean Du Port De Poncharra
发明人： Alain Chantre , Jean Du Port De Poncharra
IPC分类号： H01L218222
CPC分类号： H01L29/66272 , H01L29/732
摘要： A bipolar transistor including an extrinsic base on the surface of a silicon substrate covered by a first layer of doped polycrystalline silicon, an intrinsic base that is separated from the extrinsic base and covered by a second layer of polycrystalline silicon that constitutes the emitter and that is insulated from the first layer of polycrystalline silicon, and a link base that links the extrinsic base to the intrinsic base. The link base is located under the first layer of doped polycrystalline silicon.
摘要翻译：一种双极晶体管，包括在由第一掺杂多晶硅层覆盖的硅衬底的表面上的非本征基极，本征基极与外部基极分离并由构成发射极的第二多晶硅层覆盖，与第一层多晶硅绝缘，以及将外部基极连接到本征基底的连接基底。链路基座位于第一层掺杂多晶硅下面。

9. 发明授权

US5367184A Vertical JFET transistor with optimized bipolar operating mode and corresponding method of fabrication 失效
标题翻译：具有优化双极性工作模式和相应制造方法的垂直JFET晶体管
公开(公告)号：US5367184A
公开(公告)日：1994-11-22
申请号：US87427
申请日：1993-07-02
申请人： Alain Chantre
发明人： Alain Chantre
IPC分类号： H01L21/331 , H01L21/337 , H01L29/737 , H01L29/808 , H01L29/161 , H01L29/205 , H01L29/225
CPC分类号： H01L29/66916 , H01L29/66242 , H01L29/7371 , H01L29/8083
摘要： The vertical junction field-effect transistor comprises a semiconductor structure including an internal semiconductor layer (23, 26) extending within the channel region (7) between the gate region (4, 31), this internal layer being produced in a semiconductor material, having an energy gap (Eg.sup.2) smaller than that of the material forming the channel and gate regions, and the same type of conductivity (N) as that of the channel region, and the heterojunction formed between this internal layer and the channel region exhibits a band discontinuity situated in the valence band in the case of a N-type channel, or in the conduction band in the case of a P-type channel.
摘要翻译：垂直结场效应晶体管包括半导体结构，其包括在栅极区域（4,31）之间的沟道区域（7）内延伸的内部半导体层（23,26），该内部层由半导体材料制成，具有比形成沟道和栅极区域的材料小的能隙（Eg2）和与沟道区域相同类型的导电率（N），并且在该内部层和沟道区域之间形成的异质结带呈现带状在N型通道的情况下位于价带中的不连续性，或者在P型通道的情况下在导带中。

10. 发明授权

US07226844B2 Method of manufacturing a bipolar transistor with a single-crystal base contact 有权
标题翻译：制造具有单晶基极接触的双极晶体管的方法
公开(公告)号：US07226844B2
公开(公告)日：2007-06-05
申请号：US11091950
申请日：2005-03-28
申请人： Alain Chantre , Pascal Chevalier
发明人： Alain Chantre , Pascal Chevalier
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： A method forms a bipolar transistor in a semiconductor substrate of a first conductivity type. The method includes: forming on the substrate a single-crystal silicon-germanium layer; forming a heavily-doped single-crystal silicon layer of a second conductivity type; forming a silicon oxide layer; opening a window in the silicon oxide and silicon layers; forming on the walls of the window a silicon nitride spacer; removing the silicon-germanium layer from the bottom of the window; forming in the cavity resulting from the previous removal a heavily-doped single-crystal semiconductor layer of the second conductivity type; and forming in said window the emitter of the transistor.
摘要翻译：一种方法在第一导电类型的半导体衬底中形成双极晶体管。该方法包括：在衬底上形成单晶硅锗层; 形成第二导电类型的重掺杂单晶硅层; 形成氧化硅层; 在硅氧化物和硅层中开一个窗口; 在窗的壁上形成氮化硅间隔物; 从窗户的底部去除硅 - 锗层; 在先前去除的过程中形成在第二导电类型的重掺杂单晶半导体层的空腔中; 并在所述窗口中形成晶体管的发射极。

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