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1. 发明授权

US5359709A Apparatus and method for providing multiple operating configurations in data circuit terminating equipment 失效
标题翻译：在数据电路终端设备中提供多种操作配置的装置和方法
公开(公告)号：US5359709A
公开(公告)日：1994-10-25
申请号：US826504
申请日：1992-01-27
申请人： Alain Blanc , Sylvie Gohl-Roux , Gottfried Ungerboeck
发明人： Alain Blanc , Sylvie Gohl-Roux , Gottfried Ungerboeck
IPC分类号： H04L5/00 , H04L27/00 , H04L29/06 , H04L29/10 , G06F13/42
CPC分类号： H04L29/06 , H04L27/00
摘要： Multiple operating configurations in data circuit terminating equipment (DCE) are enabled through multiple queues stored in a random access memory and which are loaded with bits and characters coming either from data terminating equipment (DTE) or the telecommunications line. The DSP processor stores bits provided by a transmit circuit in a first queue, determines characters from the bits stored in the first queue based on a first transmission protocol and stores the characters in a second queue. A third queue is used by a control processor to store characters to be transmitted to a remote DCE. The DSP processor determines bits to be transmitted from the characters stored in a third queue based on a second transmission protocol, and stores those bits in a fourth queue. When the DCE is operating in a synchronous mode, the DSP processor determines PCM words for transmission based on the contents of the second queue and stores them in a fifth queue for transmission. Similarly, when the DCE switches to an asynchronous mode, the DSP processor determines PCM words based on the contents of the fourth queue and stores them in the fifth queue for transmission. A similar queue arrangement is provided for the receive circuitry of the DCE.
摘要翻译：数据电路终端设备（DCE）中的多种操作配置通过存储在随机存取存储器中的多个队列启用，并且装载有来自数据终端设备（DTE）或电信线路的位和字符。 DSP处理器将由发送电路提供的位在第一队列中存储，基于第一传输协议从存储在第一队列中的比特确定字符，并将该字符存储在第二队列中。控制处理器使用第三个队列来存储要发送到远程DCE的字符。 DSP处理器基于第二传输协议确定从存储在第三队列中的字符发送的比特，并将这些比特存储在第四队列中。当DCE工作在同步模式时，DSP处理器根据第二个队列的内容来确定用于传输的PCM字，并将其存储在第五个队列中进行传输。类似地，当DCE切换到异步模式时，DSP处理器基于第四队列的内容来确定PCM字，并将它们存储在第五队列中以进行传输。为DCE的接收电路提供了类似的队列布置。

2. 发明授权

US5315622A Data circuit terminating equipment (DCE) including timing arrangements circuits controlled by processing means 失效
标题翻译：数据电路终端设备（DCE），包括由处理装置控制的定时装置电路
公开(公告)号：US5315622A
公开(公告)日：1994-05-24
申请号：US754104
申请日：1991-09-03
申请人： Jean-Claude Abbiate , Alain Blanc , Gottfried Ungerboeck
发明人： Jean-Claude Abbiate , Alain Blanc , Gottfried Ungerboeck
IPC分类号： H04L7/02 , H04L7/033 , H04L27/00 , H04L27/24 , H04L29/10 , H04L7/00
CPC分类号： H04L27/24 , H04L27/00 , H04L7/0331
摘要： Data Circuit Terminating Equipment (DCE) allows the connection of a Data Terminal Equipment (DTE) to a telecommunication line. The DCE includes timing elements for providing the DTE with any desired transmitter signal element timing and any desired receiver signal element timing. The timing elements include processing elements for computing a sequence of digital values A(n) and for deriving therefrom a corresponding sequence of interrupt signals T(n). The receiver signal element timing, the transmitter signal element timing, the transmit sampling clock pulsing the D/A converter and the receive sampling clock pulsing the A/D converter are all controlled by different sequences of digital values computed by the processing elements. By generating appropriate sequences of digital values, the processing elements can provide any desired relationship between the different clocks to satisfy a transmit signal element timing slaved to the receiver signal element timing in synchronous mode, or on an external clock in tailing mode. The timing elements can also provide a transmit sampling clock slaved to the receive sampling clock in order to perform powerful digital echo cancellation techniques. Moreover, the processing elements can control the persistence of a received bit, which if a STOP bit, can allow the compensation of the DTE and the line data throughput difference.
摘要翻译：数据电路终端设备（DCE）允许将数据终端设备（DTE）连接到电信线路。 DCE包括用于向DTE提供任何期望的发射机信号元素定时和任何期望的接收机信号元素定时的定时元件。定时元件包括用于计算数字值A（n）的序列的处理元件，并由此导出相应的中断信号序列T（n）。接收器信号元件定时，发送器信号元件定时，脉冲D / A转换器的发送采样时钟和脉冲A / D转换器的接收采样时钟都由处理元件计算的不同数字值序列控制。通过产生数字值的适当序列，处理元件可以在不同时钟之间提供任何期望的关系，以满足在同步模式下或者在拖尾模式下的外部时钟在从属于接收机信号元件定时的发射信号元素定时。定时元件还可以提供从属于接收采样时钟的发射采样时钟，以执行强大的数字回波消除技术。此外，处理元件可以控制接收位的持续性，如果STOP位可以允许补偿DTE和线数据吞吐量差。

3. 发明授权

US08503540B2 Low density parity check (LDPC) encoded higher order modulation 失效
标题翻译：低密度奇偶校验（LDPC）编码高阶调制
公开(公告)号：US08503540B2
公开(公告)日：2013-08-06
申请号：US13620468
申请日：2012-09-14
申请人： Lin He , Thomas J. Kolze , Ba-Zhong Shen , Gottfried Ungerboeck , Bruce J. Currivan
发明人： Lin He , Thomas J. Kolze , Ba-Zhong Shen , Gottfried Ungerboeck , Bruce J. Currivan
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： H04L27/3416 , H03M13/253 , H04L1/0057 , H04L1/0065 , H04L27/36
摘要： A method and apparatus is disclosed to map a sequence of data to Quadrature Amplitude Modulation (QAM) constellation symbols. The method and apparatus encodes only a portion of the sequence of data and leaves a remaining portion of the sequence of data unencoded. The encoded portion of the sequence of data and the remaining unencoded portion of the sequence of data are then mapped into modulation symbols of the QAM constellation. The encoded portion of the sequence of data selects subsets of the QAM constellation, and the remaining unencoded portion of the sequence of data determines a specific modulation symbol within each subset of the QAM constellation.
摘要翻译：公开了一种将数据序列映射到正交幅度调制（QAM）星座符号的方法和装置。该方法和装置仅对该数据序列的一部分进行编码，并留下未被编码的数据序列的剩余部分。然后将数据序列的编码部分和数据序列的剩余未编码部分映射到QAM星座图的调制符号中。数据序列的编码部分选择QAM星座的子集，并且数据序列的剩余未编码部分确定QAM星座图的每个子集内的特定调制符号。

4. 发明授权

US08437366B2 Method and system for 10GBASE-T start-up 有权
标题翻译： 10GBASE-T启动的方法和系统
公开(公告)号：US08437366B2
公开(公告)日：2013-05-07
申请号：US13099760
申请日：2011-05-03
申请人： Gottfried Ungerboeck , Scott Powell
发明人： Gottfried Ungerboeck , Scott Powell
IPC分类号： H04J3/00 , H04L12/26
CPC分类号： H04L41/08 , H04L12/403
摘要： Certain aspects for the start-up procedure of transceivers supporting higher data rates over twisted-pair copper cabling are provided for 10 Gbit/sec Ethernet links (10GBASE-T). During a PMA (physical medium attachment) training period of the start-up procedure, long PMA training frames are exchanged periodically between link partners. A significant portion of each PMA training frame consists of known pseudo random sequences simultaneously transmitted over four wire pairs. PMA training frames include an InfoField for exchanging parameters and control information between link partners. For example, the InfoField's payload comprises fields for indicating current transmit power backoff (PBO), next PBO, requested PBO, transition count, control information, and for communicating precoder coefficients. Information in InfoFields is repeated and is not necessary that a link partner decodes every InfoField. For example, by occasionally reading the transition count, a link partner can determine when a change in transmit PBO and/or a state transition is to occur.
摘要翻译：为10Gbit /秒以太网链路（10GBASE-T）提供了通过双绞铜缆布线支持更高数据速率的收发器的启动过程的某些方面。在启动程序的PMA（物理介质附加）训练期间，长链PMA训练帧在链路伙伴之间定期交换。每个PMA训练帧的重要部分由通过四个线对同时传输的已知伪随机序列组成。 PMA培训框架包括用于在链接伙伴之间交换参数和控制信息的InfoField。例如，InfoField的有效载荷包括用于指示当前发送功率回退（PBO），下一个PBO，所请求的PBO，转移计数，控制信息以及用于传达预编码器系数的字段。 InfoFields中的信息被重复，链接伙伴不需要对每个InfoField进行解码。例如，通过偶尔读取转换计数，链路伙伴可以确定何时发生传输PBO和/或状态转换的变化。

5. 发明授权

US07460595B2 System and method for Huffman shaping in a data communication system 有权
标题翻译：数据通信系统中霍夫曼整形的系统和方法
公开(公告)号：US07460595B2
公开(公告)日：2008-12-02
申请号：US11188301
申请日：2005-07-25
申请人： Gottfried Ungerboeck , Arthur J. Carlson
发明人： Gottfried Ungerboeck , Arthur J. Carlson
IPC分类号： H04B1/66
CPC分类号： H04L27/3405 , H03M7/40
摘要： In a communication system, Huffman coding techniques are used to obtain shaping gains for an improvement in data transmission rates. More particularly, a novel method of Huffman shaping is described that achieves a shaping gain of greater than 1 dB. The shaping gain results in a higher data rate transmission in a communication system where transmitted power is constrained.
摘要翻译：在通信系统中，使用霍夫曼编码技术获得整形增益以提高数据传输速率。更具体地，描述了一种实现霍夫曼整形的新方法，其实现了大于1dB的整形增益。整形增益导致传输功率受限的通信系统中的较高数据速率传输。

6. 发明授权

US07457364B2 Subdimensional single-carrier modulation 有权
标题翻译：次维单载波调制
公开(公告)号：US07457364B2
公开(公告)日：2008-11-25
申请号：US10909661
申请日：2004-08-02
申请人： Gottfried Ungerboeck
发明人： Gottfried Ungerboeck
IPC分类号： H04L27/00
CPC分类号： H04L25/03343 , H04L25/03038 , H04L25/49 , H04L27/3405 , H04L2025/03375 , H04L2025/03477
摘要： A method for modulating a sequence of data symbols such that the transmit signal exhibits spectral redundancy. Null symbols are inserted in the sequence of data symbols such that a specified pattern of K data symbols and N−K null symbols is formed in every period of N symbols in the modulated sequence, N and K being positive integers and K being smaller than N.
摘要翻译：一种用于调制数据符号序列使得发送信号表现出频谱冗余的方法。在数据符号序列中插入空符号，使得在调制序列中的N个符号的每个周期中形成K个数据符号和N-K个空符号的指定模式，N和K是正整数，K小于N.

7. 发明申请

US20050141460A9 Cancellation of interference in a communication system with application to S-CDMA 有权
标题翻译：消除应用于S-CDMA的通信系统中的干扰
公开(公告)号：US20050141460A9
公开(公告)日：2005-06-30
申请号：US10142189
申请日：2002-05-08
申请人： Bruce Currivan , Thomas Kolze , Gottfried Ungerboeck , Nabil Yousef
发明人： Bruce Currivan , Thomas Kolze , Gottfried Ungerboeck , Nabil Yousef
IPC分类号： H04B1/707 , H04B7/216 , H04J13/00 , H04J13/16
CPC分类号： H04B7/216 , H04B1/71 , H04B1/7102 , H04B1/7105 , H04B1/7107 , H04J13/0003 , H04J13/16
摘要： Cancellation of interference in a communication system with application to S-CDMA. A relatively straight-forward implemented, and computationally efficient approach of selecting a predetermined number of unused codes is used to perform weighted linear combination selectively with each of the input spread signals in a multiple access communication system. If desired, the predetermined number of unused codes is always the same in each implementation. Alternatively, the predetermined number of unused codes are selected from within a reordered code matrix using knowledge that is shared between the two ends of a communication system, such as between the CMs and a CMTS. While the context of an S-CDMA communication system having CMs and a CMTS is used, the solution is generally applicable to any communication system that seeks to cancel narrowband interference. Several embodiments are also described that show the generic applicability of the solution across a wide variety of systems.
摘要翻译：消除应用于S-CDMA的通信系统中的干扰。使用选择预定数量的未使用代码的相对简单的实现和计算上有效的方法来在多址通信系统中选择性地与每个输入扩展信号执行加权线性组合。如果需要，在每个实现中，预定数量的未使用代码总是相同的。或者，使用在诸如CM和CMTS之间的通信系统的两端之间共享的知识，从重排序代码矩阵中选择预定数量的未使用代码。虽然使用具有CM和CMTS的S-CDMA通信系统的上下文，但该解决方案通常适用于试图取消窄带干扰的任何通信系统。还描述了几个实施例，其显示了解决方案在各种系统上的通用适用性。

8. 发明授权

US5132963A Echo cancelling device providing adjustment of the echo canceller coefficients during full-duplex transmission 失效
标题翻译： ECHO取消设备在全双工传输期间提供ECHO CANCELLER系统的调整
公开(公告)号：US5132963A
公开(公告)日：1992-07-21
申请号：US522333
申请日：1990-05-11
申请人： Gottfried Ungerboeck
发明人： Gottfried Ungerboeck
IPC分类号： H04B3/23
CPC分类号： H04B3/23 , H04B3/237 , H04B3/238
摘要： In the echo-cancelling device of the invention new decision-error directed algorithms are developed which permit to maintain adaptivity of the echo coefficients and perform precise tracking of the far-end echo phase in a computationally efficent manner during full-duplex operation. The echo-cancelling device comprises an adjust device (40) performing the minimization of the mean-square error obtained as the difference between the signal at the output of the equalizer (Z) and the data-symbol decision (a), for providing the adjustment of the near echo estimator (20) coefficients, of the far echo estimator (22) coefficients, and of the phase (26) of the estimated far echo.

9. 发明授权

US4615004A Microprocessor including means for concurrently copying ALU results into selected operand register subsets and at least one main memory locations 失效
标题翻译：微处理器包括用于同时将ALU结果复制到选择的操作数寄存器子集和至少一个主存储器位置的装置
公开(公告)号：US4615004A
公开(公告)日：1986-09-30
申请号：US681047
申请日：1984-12-13
申请人： Pierre R. Chevillat , Hans P. Kaeser , Dietrich G. U. Maiwald , Gottfried Ungerboeck
发明人： Pierre R. Chevillat , Hans P. Kaeser , Dietrich G. U. Maiwald , Gottfried Ungerboeck
IPC分类号： G06F9/30 , G06F7/00 , G06F9/315 , G06F15/78 , G06F17/10 , G06F13/00
CPC分类号： G06F9/30032 , G06F15/786
摘要： A microprocessor having a single common data bus (17) to which the output (33) of the arithmetic-logic unit (11) as well as input and output of the data memory (13) are connected without intermediate buffer registers. Of the working registers (21, 23, 25, 27) connected to the ALU inputs, one group (21, 23) is loaded from the common data bus and the other group (25, 27), used as accumulators, is directly loaded from the ALU output. Specific control circuitry (51, 53, 55, 57, 59, 61) allows selective storing of ALU output values into accumulators (25, 27), and simultaneous transfer with selective scaling into another register and into an addressed memory location within the same cycle during which the instruction was executed.
摘要翻译：具有单个公共数据总线（17）的微处理器，算术逻辑单元（11）的输出（33）以及数据存储器（13）的输入和输出连接到其上，而没有中间缓冲寄存器。在连接到ALU输入的工作寄存器（21,23,25,27）中，从公共数据总线加载一组（21,23），并且用作累加器的另一组（25,27）被直接加载从ALU输出。特定控制电路（51,53,55,57,59,61）允许将ALU输出值选择性地存储到累加器（25,27）中，并且通过选择性缩放同时传送到另一个寄存器并在同一周期内的寻址存储器位置执行指令期间。

10. 发明授权

US4571734A Method and apparatus for decoding the output signal of a partial-response class-IV communication or recording-device channel 失效
标题翻译：用于解码部分响应类IV通信或记录设备信道的输出信号的方法和装置
公开(公告)号：US4571734A
公开(公告)日：1986-02-18
申请号：US520666
申请日：1983-08-05
申请人： Francois B. Dolivo , Gottfried Ungerboeck , Thomas D. Howell
发明人： Francois B. Dolivo , Gottfried Ungerboeck , Thomas D. Howell
IPC分类号： H04L25/497 , H04L25/03 , H04L25/08
CPC分类号： H04L25/03184 , H04L2025/03369 , H04L25/03203
摘要： A maximum-likelihood sequence decoder is used with a partial-response signaling system for processing sequences of sampled values from a communication channel or recording device. The partial-response signals can be duobinary, dicode, or partial-response class-IV. The maximum-likelihood decoding for each sequence can be based upon a two-state trellis. Instead of two survivor metrics for two states, only a difference metric is necessary.
摘要翻译：最大似然序列解码器与部分响应信号系统一起使用，用于处理来自通信信道或记录装置的采样值的序列。部分响应信号可以是二进制，双向或部分响应类IV。每个序列的最大似然解码可以基于两状态网格。代替两个状态的两个幸存者指标，仅需要一个差异度量。

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