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1. 发明授权

US06204527B1 Semiconductor memory device and method for producing same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06204527B1
公开(公告)日：2001-03-20
申请号：US09201913
申请日：1998-11-30
申请人： Akira Sudo , Kazumasa Sunouchi , Akihiro Nitayama
发明人： Akira Sudo , Kazumasa Sunouchi , Akihiro Nitayama
IPC分类号： H01L2972
CPC分类号： H01L27/10867 , H01L29/945
摘要： A semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second conductive type different from the first conductive type, the diffusion region being formed on the surface of the semiconductor region; a trench formed in the semiconductor substrate so as to be adjacent to the diffusion region; a capacitor insulator film formed on a portion of a side surface of the trench, which extends from a position at a predetermined depth of the trench to a bottom portion of the trench, and on a bottom surface of the trench; a storage node formed so that a surface of the storage node buried in the trench has the same depth as that of the predetermined depth; a first insulator film formed in a portion of the side surface of the trench above the position of the predetermined depth of the trench, the first insulator having a window in a region contacting the diffusion region; and a storage node electrode formed on the storage node so as to bury the trench, the uppermost surface of a region of the storage node electrode contacting the diffusion region via the window being formed of a mono-crystalline silicon region. Thus, it is possible to improve the charge holding characteristic of a memory cell without deteriorating the performance of a cell transistor.
摘要翻译：半导体存储器件包括：半导体衬底; 形成在半导体衬底中的第一导电类型的半导体区域; 与所述第一导电类型不同的第二导电类型的扩散区域，所述扩散区域形成在所述半导体区域的表面上; 形成在半导体衬底中以与扩散区相邻的沟槽; 形成在所述沟槽的侧表面的从所述沟槽的预定深度的位置延伸到所述沟槽的底部的位置的一部分上的电容器绝缘膜，以及所述沟槽的底表面; 形成为使得埋在沟槽中的存储节点的表面具有与预定深度相同的深度的存储节点; 第一绝缘体膜，形成在所述沟槽的所述预定深度的位置的所述沟槽的侧表面的一部分中，所述第一绝缘体在与所述扩散区接触的区域中具有窗口; 以及存储节点电极，形成在所述存储节点上，以便掩埋所述沟槽，所述存储节点电极的与扩散区域接触的区域的最上表面经由由单晶硅区域形成的窗口。因此，可以改善存储单元的电荷保持特性，而不会降低单元晶体管的性能。

2. 发明授权

US5640035A MOSFET having improved driving performance 失效
标题翻译：具有改善驱动性能的MOSFET
公开(公告)号：US5640035A
公开(公告)日：1997-06-17
申请号：US555550
申请日：1995-11-09
申请人： Akira Sudo , Toshiharu Watanabe
发明人： Akira Sudo , Toshiharu Watanabe
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66636 , H01L29/7834
摘要： A gate oxide film is formed on the surface of a P-type silicon substrate. A gate electrode is formed on the gate oxide film. Phosphorus is ion-implanted into the P-type silicon substrate, using the gate electrode as a mask. Thus, N.sup.- -type layers of LDD regions are formed in the P-type silicon substrate. Sidewall regions of material having a high dielectric constant are formed on both sides of the gate electrode. The P-type silicon substrate is etched downward adjacent to both the sidewall regions. N.sup.+ -type layers of source and drain regions are formed in the etched surface of the P-type silicon substrate.
摘要翻译：在P型硅衬底的表面上形成栅极氧化膜。在栅极氧化膜上形成栅电极。使用栅电极作为掩模将磷离子注入到P型硅衬底中。因此，在P型硅衬底中形成有N型层的LDD区。在栅电极的两侧形成具有高介电常数的材料的侧壁区域。 P型硅衬底相邻于两个侧壁区域被向下蚀刻。源极和漏极区的N +型层形成在P型硅衬底的蚀刻表面中。

3. 发明授权

US06746933B1 Pitcher-shaped active area for field effect transistor and method of forming same 失效
公开(公告)号：US06746933B1
公开(公告)日：2004-06-08
申请号：US09999803
申请日：2001-10-26
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

4. 发明授权

US5521407A Semiconductor memory device having cell isolation structure 失效
标题翻译：具有电池隔离结构的半导体存储器件
公开(公告)号：US5521407A
公开(公告)日：1996-05-28
申请号：US334396
申请日：1994-11-03
申请人： Yusuke Kohyama , Akira Sudo
发明人： Yusuke Kohyama , Akira Sudo
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808 , H01L27/10829
摘要： The first element separation oxide film consisting of a plurality of line-shaped portions parallel to the bit line is formed on the surface of the P-type silicon substrate. The first and second trenches are formed in that portion of the P-type silicon substrate which is located between an adjacent pair of line-shaped portions of the first element separation oxide film such that both sides of the trenches come in contact with the first element separation oxide film. A sheath plate capacitor is formed in each of the trenches. The second element separation oxide film having a thickness less than that of the first element separation oxide film is formed on that portion of the surface of the P-type silicon substrate which is located between the first and second trenches.
摘要翻译：在P型硅衬底的表面上形成由与位线平行的多个线状部分构成的第一元件分离氧化膜。第一和第二沟槽形成在P型硅衬底的位于第一元件分离氧化物膜的相邻一对线状部分之间的部分中，使得沟槽的两侧与第一元件接触分离氧化膜。在每个沟槽中形成护板电容器。在位于第一和第二沟槽之间的P型硅衬底的表面的该部分上形成厚度小于第一元件分离氧化物膜的第二元件分离氧化物膜。

5. 发明授权

US06960514B2 Pitcher-shaped active area for field effect transistor and method of forming same 失效
标题翻译：投币型场效应晶体管及其形成方法
公开(公告)号：US06960514B2
公开(公告)日：2005-11-01
申请号：US10803395
申请日：2004-03-18
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
摘要翻译：对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部区域结构。本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

6. 发明授权

US6015731A Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US6015731A
公开(公告)日：2000-01-18
申请号：US923735
申请日：1997-09-04
申请人： Yusuke Kohyama , Akira Sudo
发明人： Yusuke Kohyama , Akira Sudo
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808 , H01L27/10829
摘要： The first element separation oxide film consisting of a plurality of line-shaped portions parallel to the bit line is formed on the surface of the P-type silicon substrate. The first and second trenches are formed in that portion of the P-type silicon substrate which is located between an adjacent pair of line-shaped portions of the first element separation oxide film such that both sides of the trenches come in contact with the first element separation oxide film. A sheath plate capacitor is formed in each of the trenches. The second element separation oxide film having a thickness less than that of the first element separation oxide film is formed on that portion of the surface of the P-type silicon substrate which is located between the first and second trenches.
摘要翻译：在P型硅衬底的表面上形成由与位线平行的多个线状部分构成的第一元件分离氧化膜。第一和第二沟槽形成在P型硅衬底的位于第一元件分离氧化物膜的相邻一对线状部分之间的部分中，使得沟槽的两侧与第一元件分离氧化膜。在每个沟槽中形成护板电容器。在位于第一和第二沟槽之间的P型硅衬底的表面的该部分上形成厚度小于第一元件分离氧化物膜的第二元件分离氧化物膜。

7. 发明授权

US5555520A Trench capacitor cells for a dram having single monocrystalline capacitor electrode 失效
标题翻译：用于具有单个单晶电容器电极的电容器的沟槽电容器电池
公开(公告)号：US5555520A
公开(公告)日：1996-09-10
申请号：US353368
申请日：1994-12-02
申请人： Akira Sudo , Yusuke Kohyama , Haruhiko Koyama
发明人： Akira Sudo , Yusuke Kohyama , Haruhiko Koyama
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L29/68
CPC分类号： H01L27/10861 , H01L27/10829 , H01L29/945
摘要： The present structure is characterized by the electrode of a trench capacitor of a DRAM and a periphery thereof. A trench is formed adjacent to an N type region in a substrate. An insulating film is formed on the side wall of this trench and only a part of the insulating film around the upper portion of the trench is removed, forming a window. An N type polycrystalline silicon film of a lower capacitor electrode is formed over a region from the bottom of the trench to below the window, and a capacitor insulating film is formed on this polycrystalline silicon film. A polycrystalline silicon film which becomes a first upper capacitor electrode is formed on the capacitor insulating film, filling the trench up to the lower edge of the window. A monocrystalline silicon film which becomes a second upper capacitor electrode is formed on the latter polycrystalline silicon film in such a way as to contact an N type region, filling the upper portion of the trench. An insulating film similar to a gate insulating film on the substrate is formed on the monocrystalline silicon film.
摘要翻译：本结构的特征在于DRAM的沟槽电容器的电极及其周边。在衬底中与N型区域相邻地形成沟槽。在该沟槽的侧壁上形成绝缘膜，并且除去沟槽上部周围的仅绝缘膜的一部分，形成窗口。在从沟槽的底部到窗口的下方的区域上形成下部电容电极的N型多晶硅膜，在该多晶硅膜上形成电容绝缘膜。在电容器绝缘膜上形成成为第一上电容器电极的多晶硅膜，将沟槽填充到窗口的下边缘。在后面的多晶硅膜上形成成为第二上电容器电极的单晶硅膜，以接触填充沟槽上部的N型区域。在单晶硅膜上形成与基板上的栅极绝缘膜相似的绝缘膜。

8. 发明授权

US5384473A Semiconductor body having element formation surfaces with different orientations 失效
标题翻译：半导体体具有不同取向的元件形成面
公开(公告)号：US5384473A
公开(公告)日：1995-01-24
申请号：US953808
申请日：1992-09-30
申请人： Susumu Yoshikawa , Akira Sudo
发明人： Susumu Yoshikawa , Akira Sudo
IPC分类号： H01L21/02 , H01L21/18 , H01L21/316 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L27/11 , H01L27/02 , H01L27/04 , H01L29/04
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/187 , H01L21/31658 , H01L21/76205 , H01L21/76294 , H01L21/823892 , H01L27/0928 , H01L27/11
摘要： A semiconductor body has a first and a second element formation surface. The semiconductor body is constructed in such a manner that a first semiconductor substrate, which has a first main surface at which the plane appears, is laminated to a second semiconductor substrate, which has a second main surface at which the plane appears. Made in the first semiconductor substrate is at least one opening at which the second main surface of the second semiconductor substrate. The first main surface of the first semiconductor substrate becomes the first element formation surface of the semiconductor body, and the second main surface of the second semiconductor substrate becomes the second element formation surface of the body.
摘要翻译：半导体本体具有第一和第二元件形成表面。半导体本体被构造成使具有出现平面的第一主表面的第一半导体衬底被层压到第二半导体衬底上，第二半导体衬底具有出现平面的第二主表面。在第一半导体衬底中制造的是至少一个第二半导体衬底的第二主表面的开口。第一半导体衬底的第一主表面成为半导体本体的第一元件形成表面，第二半导体衬底的第二主表面成为主体的第二元件形成表面。

9. 发明授权

US06376324B1 Collar process for reduced deep trench edge bias 失效
标题翻译：用于减小深沟槽边缘偏置的套圈过程
公开(公告)号：US06376324B1
公开(公告)日：2002-04-23
申请号：US09602969
申请日：2000-06-23
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening , Akira Sudo
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening , Akira Sudo
IPC分类号： H01L2120
CPC分类号： H01L27/10867
摘要： Disclosed is a method to provide a new deep trench collar process which reduces encroachment of strap diffusion upon array metal oxide semiconductor field effect transistors (MOSFET's) in semiconductor devices. The invention allows a reduced effective deep trench edge bias at the top of the deep trench, without compromising storage capacitance, by maximizing the distance between the MOSFET gate conductor and the deep trench storage capacitor.
摘要翻译：公开了一种提供新的深沟槽套环工艺的方法，其减少了半导体器件中的阵列金属氧化物半导体场效应晶体管（MOSFET）上带扩散的侵入。通过使MOSFET栅极导体和深沟槽存储电容器之间的距离最大化，本发明允许在深沟槽顶部减少有效的深沟槽边缘偏压，而不损害存储电容。

10. 发明授权

US5602050A Method of making a semiconductor device with conductors on stepped substrate having planar upper surfaces 失效
标题翻译：制造具有平面上表面的台阶状基板上的导体的半导体器件的方法
公开(公告)号：US5602050A
公开(公告)日：1997-02-11
申请号：US396799
申请日：1995-03-01
申请人： Akira Sudo
发明人： Akira Sudo
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L23/52 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78 , H01L21/265 , H01L21/465 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10873 , H01L21/28123 , H01L27/105 , H01L27/10808
摘要： An element separating oxide film is formed on a P-type semiconductor substrate by means of a selective oxidation method, and then a gate oxide film is formed on the element separating oxide film by a thermal oxidation method. A gate electrode film made of an N-type polysilicon material is formed so as to extend along a step portion of the element separating oxide film on the semiconductor substrate. The upper surface of the gate electrode film is flattened by means of a surface polishing method. Then, isotropic etching is performed by using a resist pattern as a mask, thereby forming a gate electrode. Since in the method the upper surface of the gate electrode film in the flattened, the semiconductor substrate is prevented from being subject to over-etching when a gage electrode is formed, so that the changes of characteristics of MOS transistors are prevented whose gate insulative films have been becoming thinner as their elements have been finer.
摘要翻译：通过选择性氧化法在P型半导体衬底上形成元件隔离氧化膜，然后通过热氧化法在元件隔离氧化膜上形成栅极氧化膜。形成由N型多晶硅材料制成的栅电极膜，以沿半导体衬底上的元件分离氧化膜的台阶部分延伸。通过表面抛光方法使栅电极膜的上表面变平。然后，通过使用抗蚀剂图案作为掩模来进行各向同性蚀刻，从而形成栅电极。由于在该方法中，平坦化的栅电极膜的上表面，当形成量具电极时，防止了半导体衬底被过度蚀刻，从而防止了MOS晶体管的特性变化，其栅极绝缘膜已经变得越来越薄，因为它们的元素更细。

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