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1. 发明授权

US07750381B2 Semiconductor device and method of manufacturing semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07750381B2
公开(公告)日：2010-07-06
申请号：US12052284
申请日：2008-03-20
申请人： Akira Hokazono , Satoshi Inaba
发明人： Akira Hokazono , Satoshi Inaba
IPC分类号： H01L31/062
CPC分类号： H01L29/7848 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a source/drain region provided in the first epitaxially grown layer sandwiching the channel region, and having a first conductivity type impurity, a second epitaxially grown layer provided between the channel region and the first epitaxially grown layer, and provided below the gate electrode, and having a second conductivity type impurity opposite to the first conductivity type.
摘要翻译：在本发明的一个方面中，半导体器件可以包括Si衬底，通过栅极电介质层设置在半导体上的栅电极，设置在Si衬底上的第一外延生长层，设置在Si衬底下面的Si衬底中的沟道区栅电极，设置在夹着沟道区的第一外延生长层中的源极/漏极区，并且具有第一导电型杂质，设置在沟道区和第一外延生长层之间的第二外延生长层，并且在并且具有与第一导电类型相反的第二导电类型杂质。

2. 发明申请

US20080230805A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20080230805A1
公开(公告)日：2008-09-25
申请号：US12052284
申请日：2008-03-20
申请人： Akira Hokazono , Satoshi Inaba
发明人： Akira Hokazono , Satoshi Inaba
IPC分类号： H01L21/336 , H01L29/778
CPC分类号： H01L29/7848 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a source/drain region provided in the first epitaxially grown layer sandwiching the channel region, and having a first conductivity type impurity, a second epitaxially grown layer provided between the channel region and the first epitaxially grown layer, and provided below the gate electrode, and having a second conductivity type impurity opposite to the first conductivity type.
摘要翻译：在本发明的一个方面中，半导体器件可以包括Si衬底，通过栅极电介质层设置在半导体上的栅电极，设置在Si衬底上的第一外延生长层，设置在Si衬底下面的Si衬底中的沟道区栅电极，设置在夹着沟道区的第一外延生长层中的源极/漏极区，并且具有第一导电型杂质，设置在沟道区和第一外延生长层之间的第二外延生长层，并且在并且具有与第一导电类型相反的第二导电类型杂质。

3. 发明授权

US08729607B2 Needle-shaped profile finFET device 有权
标题翻译：针形轮廓finFET器件
公开(公告)号：US08729607B2
公开(公告)日：2014-05-20
申请号：US13595022
申请日：2012-08-27
申请人： Hiroshi Itokawa , Akira Hokazono
发明人： Hiroshi Itokawa , Akira Hokazono
IPC分类号： H01L29/76 , H01L29/78
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/7848
摘要： Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.
摘要翻译：提出了关于finFET半导体器件的形成的结构和方法。提出了一种finFET器件，其包括形成在衬底上的鳍状物，其中鳍状物具有针状轮廓。与在鳍上外延形成的至少一个缓冲层或掺杂层结合的针状轮廓有利于通过缓冲层或掺杂层将应变引入到鳍中。鳍可以包括在第一平面上对准的硅，而缓冲层或掺杂层中的至少一个在第二平面上生长，第一和第二平面的对准是不同的，并且被选择为使得形成缓冲层或掺杂层在散热片中产生应力。产生的应力导致应变被引入鳍状沟道区域，这可以改善沟道中的电子和/或空穴迁移率。

4. 发明申请

US20130119506A1 FORMATION OF STI TRENCHES FOR LIMITING PN-JUNCTION LEAKAGE 审中-公开
标题翻译：形成用于限制PN结泄漏的STI倾斜
公开(公告)号：US20130119506A1
公开(公告)日：2013-05-16
申请号：US13293269
申请日：2011-11-10
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L23/00
CPC分类号： H01L21/76229 , H01L2924/0002 , H01L2924/00
摘要： Methods and structure are provided to facilitate isolation of respective ground plane regions in an SOTB semiconductor device. In one aspect a shallow STI trench can be combined with Si:C or Si:C/SiGe layers to confine n-type and p-type regions. In a further aspect, Ge can be implanted at the bottom of a shallow STI trench and subsequently oxidized to form SiGe oxide thereby extending the effective isolation provided by the shallow STI trench. In an aspect, a shallow STI trench can be extended to expose an underlying layer of SiGe, wherein the SiGe is subsequently oxidized to extending the effective isolation provide by the shallow STI trench. Such aspects enable a shallow STI trench to be seamlessly filled while having an extended region of isolation.
摘要翻译：提供了方法和结构以便于SOTB半导体器件中的各个接地平面区域的隔离。在一个方面，浅STI沟槽可以与Si：C或Si：C / SiGe层组合以限制n型和p型区域。在另一方面，Ge可以注入浅STI沟槽的底部，随后被氧化以形成SiGe氧化物，从而延伸由浅STI沟槽提供的有效隔离。在一个方面，可以延伸浅的STI沟槽以暴露SiGe的下层，其中SiGe随后被氧化以延伸由浅STI沟槽提供的有效隔离。这样的方面使得能够无缝地填充浅的STI沟槽，同时具有扩展的隔离区域。

5. 发明申请

US20060063314A1 Field effect transistor and method of manufacturing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20060063314A1
公开(公告)日：2006-03-23
申请号：US11203402
申请日：2005-08-15
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L21/8232
CPC分类号： H01L21/265 , H01L21/28079 , H01L21/823842 , H01L29/4958 , H01L29/517 , H01L29/518
摘要： A field effect transistor according to one embodiment of the present invention is a field effect transistor which is supposed to be operated under a temperature condition at 300 K or less, comprising: an n-channel field effect transistor having a gate electrode formed by a gate electrode material having a work function WFn of less than 4.05. A field effect transistor according to one embodiment of the present invention is a field effect transistor which is supposed to be operated under a temperature condition at 300 K or less, comprising: a p-channel field effect transistor having a gate electrode formed by a gate electrode material having a work function WFp of more than 5.17.
摘要翻译：根据本发明的一个实施例的场效应晶体管是在300K以下的温度条件下运行的场效应晶体管，包括：n沟道场效应晶体管，具有由栅极形成的栅电极具有小于4.05的功函数WFn的电极材料。根据本发明的一个实施例的场效应晶体管是应在300K或更小的温度条件下工作的场效应晶体管，包括：具有由栅极形成的栅电极的p沟道场效应晶体管功函数WFp大于5.17的电极材料。

6. 发明授权

US06956276B2 Semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film 失效
标题翻译：具有L形/反向L形栅极侧壁绝缘膜的半导体器件
公开(公告)号：US06956276B2
公开(公告)日：2005-10-18
申请号：US10422805
申请日：2003-04-25
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L21/28 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L29/417 , H01L29/78 , H01L27/095
CPC分类号： H01L29/665 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L29/41775 , H01L29/41783 , H01L29/66515 , H01L29/6653 , H01L29/66628 , Y10S257/90
摘要： Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode and having an L-shaped/reversed L-shaped cross-sectional shape, and a semiconductor layer extending over the gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode.
摘要翻译：提供了一种半导体器件，包括形成在半导体衬底上的栅极电极，形成在栅电极两侧的源极/漏极扩散层，源极/漏极扩散层侧的栅电极侧壁和栅极侧在所述栅电极附近覆盖所述半导体衬底的上表面的一部分并且具有L形/反向的L形截面形状的半导体层绝缘膜，以及在所述栅极侧壁绝缘体上延伸的半导体层膜覆盖在栅电极附近的半导体衬底的上表面的一部分。

7. 发明授权

US06875665B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06875665B2
公开(公告)日：2005-04-05
申请号：US10611985
申请日：2003-07-03
申请人： Akira Hokazono , Yoshiaki Toyoshima
发明人： Akira Hokazono , Yoshiaki Toyoshima
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/1207 , H01L29/665 , H01L29/66628
摘要： An aspect of the present invention includes a first MOSFET having a first gate electrode formed on a first semiconductor layer in a first region of a semiconductor substrate, a first channel region formed immediately below the first gate electrode in the first semiconductor layer, a first diffusion layer constituting source/drain regions formed at both the sides of the first channel region in the first semiconductor layer, a first epitaxial layer formed on the first diffusion layer, and a first silicide layer formed on the first epitaxial layer, and a second MOSFET having a second gate electrode formed on a second semiconductor layer in a second region of the semiconductor substrate, a second channel region formed immediately below the second gate electrode in the second semiconductor layer, a second diffusion layer constituting source/drain regions formed at both the sides of the second channel region in the second semiconductor layer, and a second silicide layer formed on the second diffusion layer.
摘要翻译：本发明的一个方面包括：第一MOSFET，其形成在半导体衬底的第一区域中的第一半导体层上的第一栅电极，在第一半导体层中的第一栅电极正下方形成的第一沟道区，形成在第一半导体层中的第一沟道区的两侧的第二层构成的源极/漏极区，形成在第一扩散层上的第一外延层和形成在第一外延层上的第一硅化物层，以及第二MOSFET，形成在所述半导体衬底的第二区域中的第二半导体层上的第二栅极电极，形成在所述第二半导体层中的所述第二栅电极正下方的第二沟道区，构成在两侧形成的源/漏区的第二扩散层的第二半导体层中的第二沟道区，以及在第二半导体层上形成的第二硅化物层扩散层。

8. 发明授权

US06608354B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06608354B2
公开(公告)日：2003-08-19
申请号：US10076497
申请日：2002-02-19
申请人： Akira Hokazono , Yoshiaki Toyoshima
发明人： Akira Hokazono , Yoshiaki Toyoshima
IPC分类号： H01L2976
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/1207 , H01L29/665 , H01L29/66628
摘要： An aspect of the present invention includes a first MOSFET having a first gate electrode formed on a first semiconductor layer in a first region of a semiconductor substrate, a first channel region formed immediately below the first gate electrode in the first semiconductor layer, a first diffusion layer constituting source/drain regions formed at both the sides of the first channel region in the first semiconductor layer, a first epitaxial layer formed on the first diffusion layer, and a first silicide layer formed on the first epitaxial layer, and a second MOSFET having a second gate electrode formed on a second semiconductor layer in a second region of the semiconductor substrate, a second channel region formed immediately below the second gate electrode in the second semiconductor layer, a second diffusion layer constituting source/drain regions formed at both the sides of the second channel region in the second semiconductor layer, and a second silicide layer formed on the second diffusion layer.
摘要翻译：本发明的一个方面包括：第一MOSFET，其形成在半导体衬底的第一区域中的第一半导体层上的第一栅电极，在第一半导体层中的第一栅电极正下方形成的第一沟道区，形成在第一半导体层中的第一沟道区的两侧的第二层构成的源极/漏极区，形成在第一扩散层上的第一外延层和形成在第一外延层上的第一硅化物层，以及第二MOSFET，形成在所述半导体衬底的第二区域中的第二半导体层上的第二栅极电极，形成在所述第二半导体层中的所述第二栅电极正下方的第二沟道区，构成在两侧形成的源/漏区的第二扩散层的第二半导体层中的第二沟道区，以及在第二半导体层上形成的第二硅化物层扩散层。

9. 发明授权

US6025211A Hydrogen-terminated diamond MISFET and its manufacturing method 失效
标题翻译：氢终端金刚石MISFET及其制造方法
公开(公告)号：US6025211A
公开(公告)日：2000-02-15
申请号：US158066
申请日：1998-09-22
申请人： Takefumi Ishikura , Satoshi Yamashita , Hiroshi Kawarada , Akira Hokazono
发明人： Takefumi Ishikura , Satoshi Yamashita , Hiroshi Kawarada , Akira Hokazono
IPC分类号： H01L21/04 , H01L21/336 , H01L29/10 , H01L29/16 , H01L29/78 , H01L29/786
CPC分类号： H01L29/1602 , H01L29/1033 , H01L29/66045 , H01L29/78
摘要： On the surface of a hydrogen-terminated diamond 1 formed by terminating a surface 2 of either a homoepitaxial diamond or a heteroepitaxial diamond or a surface-flattened polycrystal diamond are formed a drain-ohmic contact 4 and a source-ohmic contact 3 of gold or platinum, an insulating layer 5 formed of silicon oxide (SiO.sub.x : 1.ltoreq.X.ltoreq.2) and a gate electrode 6 mounted on said insulating layer, and the surface other than the element forming region is set to be an insulating region being non-hydrogen-terminated, for example, oxygen-terminated, and the elements formed on said region is being isolated.
摘要翻译：在通过端接同质外延金刚石或异质外延金刚石或表面平坦多晶金刚石的表面2形成的氢终止金刚石1的表面上形成漏极 - 欧姆接触4和金 - 欧姆接触3，铂，由氧化硅（SiO x：1

10. 发明授权

US08610201B1 FinFET comprising a punch-through stopper 有权
标题翻译： FinFET包括穿通塞
公开(公告)号：US08610201B1
公开(公告)日：2013-12-17
申请号：US13587327
申请日：2012-08-16
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924
摘要： Structures and methods are presented relating to formation of finFET semiconducting devices. An approach is presented to facilitate formation of a pMOS finFET which can be combined with a nMOS finFET to form a balanced CMOS device. A Si:C layer can be utilized to suppress diffusion of group III and group V impurities, where suppression can utilize interstitial and substitutional phases. A Si:Ge layer can be utilized to facilitate determination of transition between a Si layer and a Si:C layer to enable a finFET to be formed having a required volume of fin material exposed for anticipated operation (e.g., a target Vth) of the finFET device.
摘要翻译：提出了关于finFET半导体器件的形成的结构和方法。提出了一种方法来促进pMOS finFET的形成，其可以与nMOS finFET组合以形成平衡的CMOS器件。可以使用Si：C层来抑制III族和V族杂质的扩散，其中抑制可以利用间隙和替代相。可以利用Si：Ge层来促进确定Si层和Si：C层之间的转变，以使得能够形成finFET，其具有暴露于预期操作（例如，目标Vth）的所需体积的翅片材料 finFET器件。

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