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1. 发明授权

US08610201B1 FinFET comprising a punch-through stopper 有权
标题翻译： FinFET包括穿通塞
公开(公告)号：US08610201B1
公开(公告)日：2013-12-17
申请号：US13587327
申请日：2012-08-16
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924
摘要： Structures and methods are presented relating to formation of finFET semiconducting devices. An approach is presented to facilitate formation of a pMOS finFET which can be combined with a nMOS finFET to form a balanced CMOS device. A Si:C layer can be utilized to suppress diffusion of group III and group V impurities, where suppression can utilize interstitial and substitutional phases. A Si:Ge layer can be utilized to facilitate determination of transition between a Si layer and a Si:C layer to enable a finFET to be formed having a required volume of fin material exposed for anticipated operation (e.g., a target Vth) of the finFET device.
摘要翻译：提出了关于finFET半导体器件的形成的结构和方法。提出了一种方法来促进pMOS finFET的形成，其可以与nMOS finFET组合以形成平衡的CMOS器件。可以使用Si：C层来抑制III族和V族杂质的扩散，其中抑制可以利用间隙和替代相。可以利用Si：Ge层来促进确定Si层和Si：C层之间的转变，以使得能够形成finFET，其具有暴露于预期操作（例如，目标Vth）的所需体积的翅片材料 finFET器件。

2. 发明授权

US08134159B2 Semiconductor device including a p-type transistor having extension regions in sours and drain regions and method of fabricating the same 有权
标题翻译：包括在酸和漏区域中具有延伸区域的p型晶体管的半导体器件及其制造方法
公开(公告)号：US08134159B2
公开(公告)日：2012-03-13
申请号：US12481981
申请日：2009-06-10
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L29/76
CPC分类号： H01L21/2652 , H01L21/2658 , H01L21/823807 , H01L29/105 , H01L29/1054 , H01L29/6659 , H01L29/7833 , Y10S438/931
摘要： A semiconductor device according to one embodiment includes: a semiconductor layer formed on a semiconductor substrate; a gate electrode formed on the semiconductor layer via a gate insulating film; an impurity diffusion suppression layer formed between the semiconductor substrate and the semiconductor layer and including a C-containing Si-based crystal containing a first impurity, the C-containing Si-based crystal being configured to suppress diffusion of a second impurity having a p-type conductivity type, and the C-containing Si-based crystal with the first impurity having a function of suppressing generation of fixed charge in the C-containing Si-based crystal; and p-type source/drain regions formed in the semiconductor substrate, the impurity diffusion suppression layer and the semiconductor layer in sides of the gate electrode, the p-type source/drain region having an extension region in the semiconductor layer and containing the second impurity.
摘要翻译：根据一个实施例的半导体器件包括：形成在半导体衬底上的半导体层; 通过栅极绝缘膜形成在所述半导体层上的栅电极; 形成在所述半导体衬底和所述半导体层之间并且包括含有含有第一杂质的含C的Si基晶体的杂质扩散抑制层，所述含C的Si基晶体被配置为抑制具有p- 和具有抑制含C的Si基结晶中的固定电荷的产生的功能的第一杂质的含C的Si系晶体; 形成在半导体衬底中的p型源极/漏极区域，杂质扩散抑制层和栅电极侧的半导体层，p型源极/漏极区域在半导体层中具有延伸区域并且包含第二不纯。

3. 发明授权

US07750381B2 Semiconductor device and method of manufacturing semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07750381B2
公开(公告)日：2010-07-06
申请号：US12052284
申请日：2008-03-20
申请人： Akira Hokazono , Satoshi Inaba
发明人： Akira Hokazono , Satoshi Inaba
IPC分类号： H01L31/062
CPC分类号： H01L29/7848 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a source/drain region provided in the first epitaxially grown layer sandwiching the channel region, and having a first conductivity type impurity, a second epitaxially grown layer provided between the channel region and the first epitaxially grown layer, and provided below the gate electrode, and having a second conductivity type impurity opposite to the first conductivity type.
摘要翻译：在本发明的一个方面中，半导体器件可以包括Si衬底，通过栅极电介质层设置在半导体上的栅电极，设置在Si衬底上的第一外延生长层，设置在Si衬底下面的Si衬底中的沟道区栅电极，设置在夹着沟道区的第一外延生长层中的源极/漏极区，并且具有第一导电型杂质，设置在沟道区和第一外延生长层之间的第二外延生长层，并且在并且具有与第一导电类型相反的第二导电类型杂质。

4. 发明授权

US07714364B2 Semiconductor device comprising gate electrode having arsenic and phosphorus 失效
标题翻译：包括具有砷和磷的栅电极的半导体器件
公开(公告)号：US07714364B2
公开(公告)日：2010-05-11
申请号：US11333532
申请日：2006-01-18
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L29/80
CPC分类号： H01L29/7833 , H01L21/26513 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.
摘要翻译：公开了一种半导体器件，其包括具有多晶硅膜或含有砷的多晶锗膜和第一镍硅化物层的层叠结构的栅极电极，该第一镍硅化物层依次通过栅极绝缘膜在半导体衬底的元件形成区域上形成形成在所述栅电极的侧面上的侧壁绝缘膜，在所述栅极电极的两侧部分的元件形成区域中形成有含砷的源极/漏极层和形成在所述源极/漏极层上的第二硅化镍层，栅电极中含有的砷的峰值浓度至少为源极/漏极层中含有的砷的峰值浓度的1/10。

5. 发明申请

US20090166685A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090166685A1
公开(公告)日：2009-07-02
申请号：US12340027
申请日：2008-12-19
申请人： Akira HOKAZONO
发明人： Akira HOKAZONO
IPC分类号： H01L29/78 , H01L21/38
CPC分类号： H01L21/823807 , H01L21/26513 , H01L29/1054 , H01L29/665 , H01L29/7833
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate; a first impurity diffusion suppression layer formed on the semiconductor substrate for suppressing diffusion of a channel impurity; an impurity channel layer formed on the first impurity diffusion suppression layer and containing the channel impurity; a second impurity diffusion suppression layer formed on the impurity channel layer for suppressing diffusion of the channel impurity; a channel layer formed on the second impurity diffusion suppression layer; a gate insulating film formed on the channel layer; and a gate electrode formed on the gate insulating film.
摘要翻译：根据一个实施例的半导体器件包括：半导体衬底; 形成在半导体衬底上的用于抑制沟道杂质扩散的第一杂质扩散抑制层; 形成在第一杂质扩散抑制层上并含有沟道杂质的杂质沟道层; 形成在所述杂质沟道层上的用于抑制所述沟道杂质扩散的第二杂质扩散抑制层; 形成在所述第二杂质扩散抑制层上的沟道层; 形成在沟道层上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。

6. 发明授权

US07129550B2 Fin-shaped semiconductor device 失效
标题翻译：鳍状半导体器件
公开(公告)号：US07129550B2
公开(公告)日：2006-10-31
申请号：US10775017
申请日：2004-02-09
申请人： Makoto Fujiwara , Kazunari Ishimaru , Akira Hokazono
发明人： Makoto Fujiwara , Kazunari Ishimaru , Akira Hokazono
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/41733 , H01L29/458 , H01L29/66545 , H01L29/66803 , H01L29/66818
摘要： A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).
摘要翻译：形成FinFET的主要部分即散热片的半导体层具有在x方向上长且在y方向上短的形状。翅片沿方向y的宽度在三个阶段上变化。首先，在栅极长度为Lg的栅电极之间的沟道区域中，鳍方向y的宽度为Wch。此外，与方向x上的通道区域相邻的源极/漏极扩展区域中的鳍状物的宽度方向是Wext（> Wch）。此外，与源极/漏极扩展区域相邻的源极/漏极区域中在方向x上的方向y上的鳍的宽度为Wsd（> Wext）。

7. 发明申请

US20060163675A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060163675A1
公开(公告)日：2006-07-27
申请号：US11333532
申请日：2006-01-18
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/26513 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.
摘要翻译：公开了一种半导体器件，其包括具有多晶硅膜或含有砷的多晶锗膜和第一镍硅化物层的层叠结构的栅极电极，该第一镍硅化物层依次通过栅极绝缘膜在半导体衬底的元件形成区域上形成形成在所述栅电极的侧面上的侧壁绝缘膜，在所述栅极电极的两侧部分的元件形成区域中形成有含砷的源极/漏极层和形成在所述源极/漏极层上的第二硅化镍层，栅电极中含有的砷的峰值浓度至少为源极/漏极层中含有的砷的峰值浓度的1/10。

8. 发明授权

US06927459B2 Semiconductor device having a gate electrode with a sidewall insulating film and manufacturing method thereof 失效
标题翻译：具有具有侧壁绝缘膜的栅电极的半导体器件及其制造方法
公开(公告)号：US06927459B2
公开(公告)日：2005-08-09
申请号：US10364411
申请日：2003-02-12
申请人： Akira Hokazono , Mariko Takayanagi
发明人： Akira Hokazono , Mariko Takayanagi
IPC分类号： H01L21/28 , H01L21/336 , H01L21/76 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66628 , H01L21/28052 , H01L21/28114 , H01L29/665 , H01L29/66545
摘要： A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.
摘要翻译：通过在半导体衬底上的源极和漏极区域之间形成的栅极绝缘膜提供栅电极，其中除了形成在其上部的面对源极和漏极区域的暴露部分之外的栅电极的侧壁被侧壁绝缘膜，并且在栅电极的侧壁的暴露部分上形成外延膜，但不形成在栅电极的顶表面上。形成在半导体基板上的元件隔离区域由形成在半导体基板中的第一绝缘膜和第二绝缘膜构成，该第二绝缘膜形成在第一绝缘膜的内部并且具有比第一绝缘膜的外延生长速率更低的外延生长速率，源极和漏极区域的表面被硅层覆盖，硅层的一部分延伸到第一绝缘膜的表面上。

9. 发明授权

US06436776B2 Process for fabricating a aligned LDD transistor 失效
标题翻译：制造对准的LDD晶体管的工艺
公开(公告)号：US06436776B2
公开(公告)日：2002-08-20
申请号：US09820658
申请日：2001-03-30
申请人： Takeo Nakayama , Akira Hokazono
发明人： Takeo Nakayama , Akira Hokazono
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/2652 , H01L21/2658 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.
摘要翻译：通过将栅电极的侧壁绝缘膜形成两次来形成与栅电极相邻的浅杂质扩散层，实现具有改善的短沟道效应的硅化物型MOS晶体管。首先通过与第一侧壁绝缘膜自对准来形成与源极/漏极区域的栅电极不相邻的杂质扩散层部分。在与栅电极自对准形成与栅电极相邻的杂质扩散层之后，形成第二侧壁绝缘膜。通过与第二侧壁绝缘膜自对准，在栅极电极和源极/漏极区域上形成硅化物膜。

10. 发明授权

US08729607B2 Needle-shaped profile finFET device 有权
标题翻译：针形轮廓finFET器件
公开(公告)号：US08729607B2
公开(公告)日：2014-05-20
申请号：US13595022
申请日：2012-08-27
申请人： Hiroshi Itokawa , Akira Hokazono
发明人： Hiroshi Itokawa , Akira Hokazono
IPC分类号： H01L29/76 , H01L29/78
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/7848
摘要： Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.
摘要翻译：提出了关于finFET半导体器件的形成的结构和方法。提出了一种finFET器件，其包括形成在衬底上的鳍状物，其中鳍状物具有针状轮廓。与在鳍上外延形成的至少一个缓冲层或掺杂层结合的针状轮廓有利于通过缓冲层或掺杂层将应变引入到鳍中。鳍可以包括在第一平面上对准的硅，而缓冲层或掺杂层中的至少一个在第二平面上生长，第一和第二平面的对准是不同的，并且被选择为使得形成缓冲层或掺杂层在散热片中产生应力。产生的应力导致应变被引入鳍状沟道区域，这可以改善沟道中的电子和/或空穴迁移率。

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