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1. 发明授权

US08972769B2 Data processing apparatus and control method for controlling clock frequency based on calculated frequency-to-response-time ratios 有权
标题翻译：数据处理装置和控制方法，用于根据计算出的频率响应时间比来控制时钟频率
公开(公告)号：US08972769B2
公开(公告)日：2015-03-03
申请号：US13011712
申请日：2011-01-21
申请人： Akio Nakagawa , Hisashi Ishikawa
发明人： Akio Nakagawa , Hisashi Ishikawa
IPC分类号： G06F1/04 , G06F15/16 , G06F9/30 , G06F9/40 , G06F9/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.
摘要翻译：数据处理装置包括：多个处理单元，适于根据输入的操作时钟处理数据; 以及控制单元，其适于在向所述多个处理单元提供公共频率的操作时钟时测量所述多个处理单元的响应时间，并且控制要提供给所述多个处理单元中的至少一个的所述操作时钟的频率多个处理单元，使得多个测量的响应时间变得更接近。

2. 发明申请

US20110221409A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110221409A1
公开(公告)日：2011-09-15
申请号：US13110971
申请日：2011-05-19
申请人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： G05F1/00 , H03H11/26
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

3. 发明申请

US20110197089A1 DATA PROCESSING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：数据处理装置及其控制方法
公开(公告)号：US20110197089A1
公开(公告)日：2011-08-11
申请号：US13011712
申请日：2011-01-21
申请人： Akio Nakagawa , Hisashi Ishikawa
发明人： Akio Nakagawa , Hisashi Ishikawa
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.
摘要翻译：数据处理装置包括：多个处理单元，适于根据输入的操作时钟处理数据; 以及控制单元，其适于在向所述多个处理单元提供公共频率的操作时钟时测量所述多个处理单元的响应时间，并且控制要提供给所述多个处理单元中的至少一个的所述操作时钟的频率多个处理单元，使得多个测量的响应时间变得更接近。

4. 发明授权

US07633153B2 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US07633153B2
公开(公告)日：2009-12-15
申请号：US11778516
申请日：2007-07-16
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/10
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
摘要翻译：半导体模块包括安装板。多个电源开关器件芯片通过倒装芯片接合安装在安装板上。芯片具有上表面和下表面，并且被配置为面向安装板的上表面。通过倒装芯片接合将驱动IC芯片安装在安装板上。驱动IC芯片用于驱动形成在多个功率开关器件芯片中的晶体管的栅极。多个散热构件分别位于多个功率开关器件芯片的下表面上。提供树脂构件以将单个封装中的多个功率开关器件芯片和驱动IC芯片密封。

5. 发明授权

US07503654B2 Pupil reaction ascertaining device and fatigue recovery promoting device 失效
标题翻译：瞳孔反应确定装置和疲劳恢复促进装置
公开(公告)号：US07503654B2
公开(公告)日：2009-03-17
申请号：US10593881
申请日：2005-03-16
申请人： Akio Nakagawa
发明人： Akio Nakagawa
IPC分类号： A61B3/10
CPC分类号： A61B3/032 , A61B3/0008 , A61B3/112
摘要： It is an object of the present invention to provide a pupillary reflex checking apparatus that enables a subject to check his own pupillary reflex and that keeps down cost and to provide a fatigue recovery facilitating apparatus that includes the pupillary reflex checking apparatus. The pupillary reflex apparatus of the present invention includes, as essential elements of its structure, a reflecting unit and a stimulus applying unit. Of these, the reflecting unit has a structure which includes an optical reflecting surface disposed in a plane that intersects with a visual axis of a subject such that an image of a pupil of a subject's eye is formed on the optical reflecting surface. Further, the stimulus applying unit applies a stimulus to induce the pupillary reflex in the subject. Specifically, it is possible to use a light source which gives a light stimulus to the subject's eye, such as an LED light source, an electric bulb, a strobe, or the like, as the stimulus applying unit.
摘要翻译：本发明的目的是提供一种瞳孔反射检查装置，其能够使对象检查自己的瞳孔反射并降低成本，并提供包括瞳孔反射检查装置的疲劳恢复促进装置。本发明的瞳孔反射装置包括作为其结构的基本要素的反射单元和刺激施加单元。其中，反射单元具有包括设置在与被摄体的视轴相交的平面中的光反射面的结构，使得在光反射面上形成被检眼的瞳孔图像。此外，刺激施加单元施加刺激以诱导受试者中的瞳孔反射。具体地说，作为刺激施加单元，可以使用给予对象眼睛的光刺激的光源，例如LED光源，电灯泡，闪光灯等。

6. 发明申请

US20080251838A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080251838A1
公开(公告)日：2008-10-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
摘要翻译：半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上，以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

7. 发明申请

US20080035992A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080035992A1
公开(公告)日：2008-02-14
申请号：US11836383
申请日：2007-08-09
申请人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7828
摘要： This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer.A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.
摘要翻译：该半导体器件包括形成在第一导电类型的漏极层上的第一导电类型的漂移层和电连接到漏极层的漏电极。在漂移层的表面上形成第二导电类型的半导体基底层，并且在半导体基底层中进一步形成第一导电类型的源极区。源电极电连接到源区和半导体基层。多个栅电极通过栅极绝缘膜形成，使得半导体基底层可以被栅电极夹持。被栅电极夹持的半导体基底层的宽度为0.3微米以下。

8. 发明申请

US20070242223A1 Pupil Reaction Ascertaining Device and Fatigue Recovery Promoting Device 失效
标题翻译：瞳孔反应确定装置和疲劳恢复促进装置
公开(公告)号：US20070242223A1
公开(公告)日：2007-10-18
申请号：US10593881
申请日：2005-03-16
申请人： Akio Nakagawa
发明人： Akio Nakagawa
IPC分类号： A61B5/16
CPC分类号： A61B3/032 , A61B3/0008 , A61B3/112
摘要： It is an object of the present invention to provide a pupillary reflex checking apparatus that enables a subject to check his own pupillary reflex and that keeps down cost and to provide a fatigue recovery facilitating apparatus that includes the pupillary reflex checking apparatus. The pupillary reflex apparatus of the present invention includes, as essential elements of its structure, a reflecting unit and a stimulus applying unit. Of these, the reflecting unit has a structure which includes an optical reflecting surface disposed in a plane that intersects with a visual axis of a subject such that an image of a pupil of a subject's eye is formed on the optical reflecting surface. Further, the stimulus applying unit applies a stimulus to induce the pupillary reflex in the subject. Specifically, it is possible to use a light source which gives a light stimulus to the subject's eye, such as an LED light source, an electric bulb, a strobe, or the like, as the stimulus applying unit.
摘要翻译：本发明的目的是提供一种瞳孔反射检查装置，其能够使对象检查自己的瞳孔反射并降低成本，并提供包括瞳孔反射检查装置的疲劳恢复促进装置。本发明的瞳孔反射装置包括作为其结构的基本要素的反射单元和刺激施加单元。其中，反射单元具有包括设置在与被摄体的视轴相交的平面中的光反射面的结构，使得在光反射面上形成被检眼的瞳孔图像。此外，刺激施加单元施加刺激以诱导受试者中的瞳孔反射。具体地说，作为刺激施加单元，可以使用给予对象眼睛的光刺激的光源，例如LED光源，电灯泡，闪光灯等。

9. 发明授权

US07230297B2 Trench-gated MOSFET including schottky diode therein 有权
标题翻译：沟槽栅MOSFET，其中包括肖特基二极管
公开(公告)号：US07230297B2
公开(公告)日：2007-06-12
申请号：US11127224
申请日：2005-05-12
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

10. 发明授权

US07227225B2 Semiconductor device having a vertical MOS trench gate structure 失效
标题翻译：具有垂直MOS沟槽栅极结构的半导体器件
公开(公告)号：US07227225B2
公开(公告)日：2007-06-05
申请号：US10829173
申请日：2004-04-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933
摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.
摘要翻译：在第一半导体区域上形成第二半导体区域。在第二半导体区域的一部分上形成第三半导体区域。沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。栅极绝缘膜形成在沟槽的相对的侧表面上。在栅极绝缘膜上形成第一和第二栅电极。第一和第二栅电极彼此分离。导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

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