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1. 发明授权

US4782037A Process of fabricating a semiconductor insulated circuit device having a phosphosilicate glass insulating film 失效
标题翻译：制造具有磷硅玻璃绝缘膜的半导体绝缘电路器件的工艺
公开(公告)号：US4782037A
公开(公告)日：1988-11-01
申请号：US925458
申请日：1986-10-30
申请人： Akihiro Tomozawa , Yoku Kaino , Shigeru Shimada , Nozomi Horino , Yoshiaki Yoshiura , Osamu Tsuchiya , Shozo Hosoda
发明人： Akihiro Tomozawa , Yoku Kaino , Shigeru Shimada , Nozomi Horino , Yoshiaki Yoshiura , Osamu Tsuchiya , Shozo Hosoda
IPC分类号： H01L21/768 , H01L23/532 , H01L21/441 , H01L21/473
CPC分类号： H01L23/5329 , H01L21/76889 , H01L23/53295 , H01L2924/0002
摘要： Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.
摘要翻译：这里公开了一种制造半导体集成电路器件的方法，其中形成在通过将多晶硅层与含有高熔点难熔金属的层（即，难熔金属层）或难熔金属的硅化物层和由磷硅酸盐玻璃制成的第一绝缘膜，所述第一绝缘膜流过含有难熔金属的导电层，第二绝缘膜防止含有难熔金属的层通过玻璃流从多晶硅层剥离。通过沉积形成第二绝缘膜以具有不小于预定值的厚度。

2. 发明授权

US5580810A Method of making a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US5580810A
公开(公告)日：1996-12-03
申请号：US416099
申请日：1995-04-04
申请人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
发明人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
IPC分类号： G11C11/401 , G11C5/02 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/8247
CPC分类号： H01L23/522 , G11C5/025 , H01L27/10805 , H01L2924/0002 , Y10S257/922 , Y10S257/925 , Y10S438/926
摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.
摘要翻译：一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

3. 发明授权

US6160275A Semiconductor gate array device 失效
标题翻译：半导体门阵列器件
公开(公告)号：US6160275A
公开(公告)日：2000-12-12
申请号：US692253
申请日：1996-08-05
申请人： Yoji Nishio , Yasuo Kaminaga , Isamu Kobayashi , Yoshihiko Yamamoto , Nozomi Horino , Kousaku Hirose
发明人： Yoji Nishio , Yasuo Kaminaga , Isamu Kobayashi , Yoshihiko Yamamoto , Nozomi Horino , Kousaku Hirose
IPC分类号： H01L27/118 , H01L27/10
CPC分类号： H01L27/11807
摘要： In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines. Additionally, in order to present a semiconductor integrated device having a static type RAM that has realized with its simple structure a shortening of the memory cycle, a RAM is constructed by having memory cells, in which each is composed of a pair of transfer MOSFETs, which both of the MOSFETs are turned on during the write-in operation and one of the MOSFETs is turned on during the read-out operation, is located in between a complementary data line and an input/output node that has a complementary relationship with an information storage part comprised by a pair of inverter circuits in which the inputs and outputs are mutually cross-connected. By constructing in this way, it becomes possible to speed up the write-in operation with accuracy by having a complementary write-in signal received from a pair of the complementary lines during the read-out operation, and it becomes possible to obtain read-out signals rapidly and to prevent write-in errors caused by the pre-read-out potential of the data line because the information storage part is connected only to one of the data lines through one of the transfer gates during the read-out operation.
摘要翻译：为了呈现具有高存储密度和高速逻辑电路的主片式LSI的基本单元，基本单元由每对PMOS 1，NMOS 4，PMOS 7和NMOS 10组成，并且三个接触孔 - 除了接触孔17之外，因为连接到GND电源线51和53或Vcc电源线50和52的每个MOS的MOS沟道宽度W内的接触孔形成在垂直方向上到每个电力线。此外，为了呈现具有通过其简单结构实现的具有简化结构的静态型RAM的半导体集成器件，缩短了存储器周期，RAM通过具有存储单元构成，其中每个存储单元由一对转移MOSFET组成，其中两个MOSFET在写入操作期间导通，并且在读出操作期间MOSFET中的一个导通，位于互补数据线与具有互补关系的输入/输出节点之间信息存储部分由输入和输出相互交叉连接的一对反相器电路组成。通过以这种方式构造，可以通过在读出操作期间具有从一对互补线接收的互补写入信号来准确地加速写入操作，并且可以获得读取操作，并且防止由于数据线的预读出电位引起的写入错误，因为信息存储部分在读出操作期间仅通过一个传输门连接到一条数据线。

4. 发明授权

US5416347A Semiconductor memory device with additional conductive line to prevent line breakage 失效
标题翻译：半导体存储器件具有额外的导线，可防止线路断线
公开(公告)号：US5416347A
公开(公告)日：1995-05-16
申请号：US959534
申请日：1992-10-13
申请人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
发明人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
IPC分类号： G11C11/401 , G11C5/02 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/772
CPC分类号： H01L23/522 , G11C5/025 , H01L27/10805 , H01L2924/0002 , Y10S257/922 , Y10S257/925 , Y10S438/926
摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.
摘要翻译：一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

5. 发明授权

US4830977A Method of making a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US4830977A
公开(公告)日：1989-05-16
申请号：US148956
申请日：1988-01-27
申请人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
发明人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
IPC分类号： G11C11/401 , G11C5/02 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L23/522 , G11C5/025 , H01L27/10805 , H01L2924/0002 , Y10S257/922 , Y10S257/925 , Y10S438/926
摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.
摘要翻译：一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

6. 发明授权

US4731642A Semiconductor memory device with means to prevent word line breakage 失效
标题翻译：半导体存储器件具有防止字线破损的手段
公开(公告)号：US4731642A
公开(公告)日：1988-03-15
申请号：US704572
申请日：1985-02-22
申请人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
发明人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
IPC分类号： G11C11/401 , G11C5/02 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/10 , H01L27/108 , H01L29/78 , H01L23/50 , H01L23/54 , H01L29/44
CPC分类号： H01L23/522 , G11C5/025 , H01L27/10805 , H01L2924/0002 , Y10S257/922 , Y10S257/925 , Y10S438/926
摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.
摘要翻译：一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

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