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1. 发明申请

US20070111498A1 Method of fabricating n-type semiconductor diamond, and semiconductor diamond 有权
公开(公告)号：US20070111498A1
公开(公告)日：2007-05-17
申请号：US11651502
申请日：2007-01-10
申请人： Akihiko Nambo , Takahiro Imai , Yoshiki Nishibayashi
发明人： Akihiko Nambo , Takahiro Imai , Yoshiki Nishibayashi
IPC分类号： H01L21/44
CPC分类号： C30B25/02 , C30B29/04 , H01L21/02376 , H01L21/0243 , H01L21/02433 , H01L21/02444 , H01L21/02494 , H01L21/02527 , H01L21/02576 , H01L21/02587 , H01L21/02609 , H01L21/0262 , H01L21/02658 , H01L21/041 , H01L29/66022 , H01L29/66037
摘要： An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond, obtained in the above-described way, as well as the use of p-type single-crystalline {100} diamond substrate allow for a pn junction type, a pnp junction type, an npn junction type and a pin junction type semiconductor diamond to be obtained.

2. 发明申请

US20090160307A1 DIAMOND ELECTRON SOURCE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：金刚石电子源及其制造方法
公开(公告)号：US20090160307A1
公开(公告)日：2009-06-25
申请号：US12094250
申请日：2007-09-18
申请人： Akihiko Ueda , Yoshiyuki Yamamoto , Yoshiki Nishibayashi , Takahiro Imai
发明人： Akihiko Ueda , Yoshiyuki Yamamoto , Yoshiki Nishibayashi , Takahiro Imai
IPC分类号： H01J1/16 , H01J9/02
CPC分类号： H01J1/3044 , H01J9/025 , H01J37/065 , H01J37/073 , H01J2201/30407 , H01J2201/30411 , H01J2201/30419 , H01J2201/30457 , H01J2237/06341 , H01J2237/26 , H01J2237/3137 , H01J2237/3146 , H01J2237/31749 , H01J2237/3175
摘要： A diamond electron source in which a single sharpened tip is formed at one end of a pillar-shaped diamond monocrystal of a size for which resist application is difficult in a microfabrication process, as an electron emission point used in an electron microscope or other electron beam device, and a method for manufacturing the diamond electron source. One end of a pillar-shaped diamond monocrystal 10 is ground to form a smooth flat surface 11, and a ceramic layer 12 is formed on the smooth flat surface 11. A thin-film layer 14 having a prescribed shape is deposited on the ceramic layer 12 using a focused ion beam device, after which the ceramic layer 12 is patterned by etching using the thin-film layer 14 as a mask. A single sharpened tip is formed at one end of the pillar-shaped diamond monocrystal 10 by dry etching using the resultant ceramic mask.
摘要翻译：一种金刚石电子源，其中在微细加工过程中难以施加抗蚀剂尺寸的柱状金刚石单晶的一端形成单个锐化尖端作为电子显微镜或其他电子束中使用的电子发射点器件，以及金刚石电子源的制造方法。将柱状金刚石单晶10的一端研磨成平滑的平坦面11，在平坦的平坦面11上形成陶瓷层12.具有规定形状的薄膜层14沉积在陶瓷层上 12，使用聚焦离子束装置，之后通过使用薄膜层14作为掩模的蚀刻对陶瓷层12进行图案化。通过使用所得到的陶瓷掩模的干蚀刻，在柱状金刚石单晶10的一端形成单个尖锐的尖端。

3. 发明申请

US20050202665A1 Method of fabricating n-type semiconductor diamond, and semiconductor diamond 有权
标题翻译：制造n型半导体金刚石和半导体金刚石的方法
公开(公告)号：US20050202665A1
公开(公告)日：2005-09-15
申请号：US11013450
申请日：2004-12-17
申请人： Akihiko Namba , Takahiro Imai , Yoshiki Nishibayashi
发明人： Akihiko Namba , Takahiro Imai , Yoshiki Nishibayashi
IPC分类号： C30B25/02 , C30B29/04 , H01L21/04 , H01L21/20 , H01L21/205 , H01L21/44
CPC分类号： C30B25/02 , C30B29/04 , H01L21/02376 , H01L21/0243 , H01L21/02433 , H01L21/02444 , H01L21/02494 , H01L21/02527 , H01L21/02576 , H01L21/02587 , H01L21/02609 , H01L21/0262 , H01L21/02658 , H01L21/041 , H01L29/66022 , H01L29/66037
摘要： An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond, obtained in the above-described way, as well as the use of p-type single-crystalline {100} diamond substrate allow for a pn junction type, a pnp junction type, an npn junction type and a pin junction type semiconductor diamond to be obtained.
摘要翻译：通过处理单晶{100}金刚石衬底10以形成{111}面，然后通过使金刚石外延生长同时n掺杂金刚石{111}面而形成n型金刚石外延层20 。此外，以上述方式获得的n型半导体金刚石，p型半导体金刚石和非掺杂金刚石以及使用p型单晶{100}金刚石衬底的组合允许对于pn结型，pnp结型，npn结型和pin结型半导体金刚石。

4. 发明授权

US06709730B2 Method of making diamond product and diamond product 失效
标题翻译：制造钻石产品和钻石产品的方法
公开(公告)号：US06709730B2
公开(公告)日：2004-03-23
申请号：US09995854
申请日：2001-11-29
申请人： Yoshiki Nishibayashi , Kiichi Meguro , Takahiro Imai , Yutaka Ando
发明人： Yoshiki Nishibayashi , Kiichi Meguro , Takahiro Imai , Yutaka Ando
IPC分类号： B32B900
CPC分类号： H01J9/025 , C30B29/04 , C30B33/00 , H01J1/3044 , Y10T428/24355 , Y10T428/24628 , Y10T428/30
摘要： The method of making a diamond product in accordance with the present invention comprises the steps of forming a diamond substrate (50) with a mask layer (52), and etching the diamond substrate (50) formed with the mask layer (52) with a plasma of a mixed gas composed of a gas containing an oxygen atom and a gas containing a fluorine atom, whereas the fluorine atom concentration is within the range of 0.04% to 6% with respect to the total number of atoms in the mixed gas.
摘要翻译：制造根据本发明的金刚石产品的方法包括以下步骤：用掩模层（52）形成金刚石基底（50），并用形成有掩模层（52）的金刚石基底（50）蚀刻由含有氧原子的气体和含有氟原子的气体组成的混合气体的等离子体，而氟原子浓度相对于混合气体中的原子总数为0.04〜6％的范围。

5. 发明授权

US08119241B2 Method for manufacturing diamond monocrystal having a thin film, and diamond monocrystal having a thin film 有权
标题翻译：具有薄膜的金刚石单晶的制造方法和具有薄膜的金刚石单晶
公开(公告)号：US08119241B2
公开(公告)日：2012-02-21
申请号：US12282137
申请日：2007-12-26
申请人： Akihiko Ueda , Kiichi Meguro , Yoshiyuki Yamamoto , Yoshiki Nishibayashi , Takahiro Imai
发明人： Akihiko Ueda , Kiichi Meguro , Yoshiyuki Yamamoto , Yoshiki Nishibayashi , Takahiro Imai
IPC分类号： C30B29/04
CPC分类号： C30B29/04 , C30B25/02 , C30B25/105 , H01L21/02376 , H01L21/02433 , H01L21/02527 , H01L21/02576 , H01L21/02609 , H01L21/0262 , Y10T428/24355 , Y10T428/30
摘要： A method for growing a low-resistance phosphorus-doped epitaxial thin film having a specific resistance of 300 Ωcm or less at 300 K on a principal surface of a {111} monocrystal substrate under conditions in which the phosphorus atom/carbon atom ratio is 3% or higher, includes the principal surface having an off-angle of 0.50° or greater. The diamond monocrystal having a low-resistance phosphorus-doped diamond epitaxial thin film is such that the thin-film surface has an off-angle of 0.50° or greater with respect to the {111} plane, and the specific resistance of the low-resistance phosphorus-doped diamond epitaxial thin film is 300 Ωcm or less at 300 K.
摘要翻译：一种在{111}单晶衬底的主表面上在300K下比电阻为300Ω·cm-cm或更小的低电阻磷掺杂外延薄膜的方法，其中磷原子/碳原子比为3％以上，主偏离角为0.50°以上的主表面。具有低电阻磷掺杂金刚石外延薄膜的金刚石单晶使得薄膜表面相对于{111}面具有0.50°或更大的偏角，并且低电阻磷掺杂金刚石外延薄膜的电阻率电阻磷掺杂金刚石外延薄膜在300K时为300＆OHgr; cm以下。

6. 发明授权

US07534360B2 Method of making diamond product and diamond product 失效
公开(公告)号：US07534360B2
公开(公告)日：2009-05-19
申请号：US10774417
申请日：2004-02-10
申请人： Yoshiki Nishibayashi , Kiichi Meguro , Takahiro Imai , Yutaka Ando
发明人： Yoshiki Nishibayashi , Kiichi Meguro , Takahiro Imai , Yutaka Ando
IPC分类号： C23F1/00
CPC分类号： H01J9/025 , C30B29/04 , C30B33/00 , H01J1/3044 , Y10T428/24355 , Y10T428/24628 , Y10T428/30
摘要： The method of making a diamond product in accordance with the present invention comprises the steps of forming a diamond substrate (50) with a mask layer (52), and etching the diamond substrate (50) formed with the mask layer (52) with a plasma of a mixed gas composed of a gas containing an oxygen atom and a gas containing a fluorine atom, whereas the fluorine atom concentration is within the range of 0.04% to 6% with respect to the total number of atoms in the mixed gas.

7. 发明授权

US07476895B2 Method of fabricating n-type semiconductor diamond, and semiconductor diamond 有权
标题翻译：制造n型半导体金刚石和半导体金刚石的方法
公开(公告)号：US07476895B2
公开(公告)日：2009-01-13
申请号：US11651502
申请日：2007-01-10
申请人： Akihiko Namba , Takahiro Imai , Yoshiki Nishibayashi
发明人： Akihiko Namba , Takahiro Imai , Yoshiki Nishibayashi
IPC分类号： H01L29/04 , H01L31/20 , H01L31/036 , H01L31/0376
CPC分类号： C30B25/02 , C30B29/04 , H01L21/02376 , H01L21/0243 , H01L21/02433 , H01L21/02444 , H01L21/02494 , H01L21/02527 , H01L21/02576 , H01L21/02587 , H01L21/02609 , H01L21/0262 , H01L21/02658 , H01L21/041 , H01L29/66022 , H01L29/66037
摘要： An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond, obtained in the above-described way, as well as the use of p-type single-crystalline {100} diamond substrate allow for a pn junction type, a pnp junction type, an npn junction type and a pin junction type semiconductor diamond to be obtained.
摘要翻译：通过处理单晶{100}金刚石衬底10以形成{111}面，然后通过使金刚石外延生长同时n掺杂金刚石{111}面而形成n型金刚石外延层20 。此外，以上述方式获得的n型半导体金刚石，p型半导体金刚石和非掺杂金刚石以及使用p型单晶{100}金刚石衬底的组合允许对于pn结型，pnp结型，npn结型和pin结型半导体金刚石。

8. 发明授权

US07432521B2 Logical operation element field emission emitter and logical operation circuit 失效
标题翻译：逻辑运算元件场发射器和逻辑运算电路
公开(公告)号：US07432521B2
公开(公告)日：2008-10-07
申请号：US10526471
申请日：2004-03-05
申请人： Natsuo Tatsumi , Yoshiki Nishibayashi , Takahiro Imai , Tsuneo Nakahara
发明人： Natsuo Tatsumi , Yoshiki Nishibayashi , Takahiro Imai , Tsuneo Nakahara
IPC分类号： H01L29/06
CPC分类号： H03K19/06 , H01J19/24 , H01J21/20 , H03K19/08
摘要： A logical operation element and logical operation circuit are provided that are capable of high speed and a high degree of integration.A logical operation circuit has a construction wherein, in a logical operation element, the anodes of first and second field emission type microfabricated electron emitters are put at the same potential and two or more signal voltages are input to gate electrodes corresponding to these emitters. A NOR element so arranged that when a high potential input signal is input to either of the two lines, electron emission occurs from the emitters and the potential of said anodes is lowered, and a NAND element wherein the cathodes of the first and second field emission type microfabricated electron emitters are connected in series, two signal voltages are applied to the gate electrodes corresponding to the first and second emitter and the anode potential of the second emitter is lowered when the two input signals are high potential are employed.
摘要翻译：提供了能够高速度和高集成度的逻辑运算元件和逻辑运算电路。逻辑运算电路具有这样的结构，其中在逻辑运算元件中，将第一和第二场致发射型微细加电子发射体的阳极置于相同的电位，并将两个或更多个信号电压输入到对应于这些发射极的栅电极。一种NOR元件，其被布置成当高电位输入信号被输入到两条线中的任一条时，从发射极发生电子发射，并且所述阳极的电位降低;以及NAND元件，其中第一和第二场致发射的阴极类型的微制造电子发射体串联连接时，两个信号电压施加到对应于第一和第二发射极的栅电极，并且当采用两个输入信号为高电位时，第二发射极的阳极电位降低。

9. 发明申请

US20080164802A1 Diamond Electron Emission Cathode, Electron Emission Source, Electron Microscope, And Electron Beam Exposure Device 审中-公开
标题翻译：金刚石电子发射阴极，电子发射源，电子显微镜和电子束曝光装置
公开(公告)号：US20080164802A1
公开(公告)日：2008-07-10
申请号：US11665455
申请日：2006-06-19
申请人： Yoshiki Nishibayashi , Akihiko Uedo , Yoshiyuki Yamamoto , Takahiro Imai
发明人： Yoshiki Nishibayashi , Akihiko Uedo , Yoshiyuki Yamamoto , Takahiro Imai
IPC分类号： H01J1/14 , H01L29/16
CPC分类号： H01J1/15 , H01J1/14 , H01J37/06 , H01J2237/06308 , H01J2237/06316
摘要： An object of the present invention is to provide an electron emission cathode and an electron emission source using diamond and having a high brightness and a small energy width that are used in electron beam and electron beam devices and vacuum tubes, in particular, electron microscopes and electron beam exposure devices, and electronic devices that uses such electron emission cathode and electron emission source. A diamond electron emission cathode according to the present invention has single crystal diamond in at least part thereof, the diamond electron emission cathode being in a columnar form having a sharpened acute section in one place of an electron emitting portion and being constituted by at least two types of semiconductors that differ in electric properties. One of the types constituting the semiconductors is a n-type semiconductor comprising n-type impurities at 2×1015 cm−3 or higher, the other type is a p-type semiconductor comprising p-type impurities at 2×1015 cm−3 or higher, the p-type semiconductor and the n-type semiconductor are joined, an electric potential that is negative with respect to the p-type semiconductor is applied with a pair of current introducing terminals to the n-type semiconductor so that electrons flow from the n-type semiconductor to the p-type semiconductor, and the n-type semiconductor has a component in which electrons flow to the electron emitting portion.
摘要翻译：本发明的目的是提供一种使用金刚石的电子发射阴极和电子发射源，并且具有用于电子束和电子束装置以及真空管，特别是电子显微镜的高亮度和小的能量宽度电子束曝光装置和使用这种电子发射阴极和电子发射源的电子装置。根据本发明的金刚石电子发射阴极在其至少一部分中具有单晶金刚石，金刚石电子发射阴极呈柱形，在一个电子发射部分的位置具有锐化的锐角部分，并且由至少两个电性能不同的半导体类型。构成半导体的类型之一是包括2×10 15 -3 -3以上的n型杂质的n型半导体，另一种是p型半导体包括2×10 15 cm -3以上的p型杂质，p型半导体和n型半导体接合，相对于向p型半导体施加一对电流引入端子到n型半导体，使得电子从n型半导体流向p型半导体，并且n型半导体具有其中电子流向电子发射部分。

10. 发明申请

US20080044647A1 Method for Forming Carbonaceous Material Protrusion and Carbonaceous Material Protrusion 审中-公开
标题翻译：形成碳质材料突起和碳质材料突起的方法
公开(公告)号：US20080044647A1
公开(公告)日：2008-02-21
申请号：US10594718
申请日：2005-03-24
申请人： Yoshiki Nishibayashi , Tomihito Miyazaki , Tetsuya Hattori , Takahiro Imai
发明人： Yoshiki Nishibayashi , Tomihito Miyazaki , Tetsuya Hattori , Takahiro Imai
IPC分类号： H01J9/02 , B82B3/00 , G01N13/16 , H01J1/304
CPC分类号： B81C1/00111 , H01J9/025 , H01J2329/0415 , H01J2329/0447 , Y10T428/26
摘要： This method of forming a carbonaceous material projection structure includes: the step of applying a resist 11 onto a diamond substrate 10; the step of forming holes 12 in the applied resist 11, the holes 12 being provided according to a predetermined arrangement, a wall 12b of each of the holes 12 being inversely tapered from an aperture 12a toward a bottom; the step of depositing a mask material through the aperture 12a to form a mask deposition 14 in each of the holes 12; the step of lifting off a mask material 13 deposited on the resist 11 together with the resist 11; and etching the diamond substrate 10 using the mask deposition 14 as a mask to form a carbonaceous material projection.
摘要翻译：这种形成碳质材料投影结构的方法包括：将抗蚀剂11涂覆在金刚石基板10上的步骤; 在施加的抗蚀剂11中形成孔12的步骤，孔12根据预定布置设置，每个孔12的壁12b从孔12a向底部呈倒锥形; 通过孔12a沉积掩模材料以在每个孔12中形成掩模沉积14的步骤; 剥离与抗蚀剂11一起沉积在抗蚀剂11上的掩模材料13的步骤; 并使用掩模沉积14作为掩模蚀刻金刚石基板10，以形成碳质材料凸起。

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