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1. 发明授权

US4734877A Vector processing system 失效
标题翻译：矢量处理系统
公开(公告)号：US4734877A
公开(公告)日：1988-03-29
申请号：US15625
申请日：1987-02-17
申请人： Akiharu Sakata , Shunichi Torii , Yoshifumi Takamoto
发明人： Akiharu Sakata , Shunichi Torii , Yoshifumi Takamoto
IPC分类号： G06F17/16 , G06F7/24 , G06F15/78 , G06F15/347
CPC分类号： G06F15/8053 , G06F7/24
摘要： A vector processing system including a main storage for storing vector instructions and vector data, an instruction register for holding a vector instruction read out of the main storage, a decoder for decoding the vector instruction held in the instruction register, and an execution unit, operative to implement a vector operation in response to an output of the decoder, including a facility which, when a sort instruction inclusive of a vector starting address, increment switching parameter and an operation switching parameter has been set up in the instruction register, implements a sorting process specified by the instruction for vector data stored in the main storage, the facility including a circuit in which the operation switching parameter is set and which produces an operation switching signal in compliance with the number of operations and the position of a vector element to be operated, a circuit in which the increment switching parameter is set and which produces an increment switching signal in compliance with the position of the vector element to be operated, a fetch/store address generating circuit in which the vector starting address and increment switching parameter are set and which in compliance with these settings generates addresses of vector elements to be sorted for reading out and writing in the main storage successively in an incremental manner and generates the addresses with their incremental value being changed in compliance with the increment switching signal, and an operation circuit which implements an operation for sorting vector elements read out of the main storage in compliance with the operation switching signal, the facility implementing sorting for all elements of vector data to be sorted when the sort instruction is set up in the instruction register.
摘要翻译：一种矢量处理系统，包括用于存储矢量指令和矢量数据的主存储器，用于保持从主存储器读出的矢量指令的指令寄存器，用于解码保存在指令寄存器中的矢量指令的解码器，以及执行单元，以响应于解码器的输出来执行向量操作，包括当在指令寄存器中已经建立了包括向量起始地址，增量切换参数和操作切换参数的排序指令时，执行排序由存储在主存储器中的矢量数据的指令指定的处理，该设备包括其中设置了操作切换参数的电路，并且根据操作次数和矢量元素的位置产生操作切换信号其中增加切换参数被设置并产生增量的电路根据要操作的矢量元件的位置的切换信号，设置向量起始地址和增量切换参数的获取/存储地址生成电路，并且其符合这些设置生成要排序的向量元素的地址在主存储器中以增量方式连续地读出和写入，并且根据增量切换信号生成其增量值被改变的地址，以及执行用于对从主存储器读出的向量元素进行排序的操作的操作电路符合操作切换信号，当在指令寄存器中设置排序指令时，设施对所有要分类的矢量数据元素进行排序。

2. 发明授权

US4885678A Vector processor for processing database without special tags for vector elements 失效
标题翻译：用于处理数据库的矢量处理器，无需矢量元素的特殊标签
公开(公告)号：US4885678A
公开(公告)日：1989-12-05
申请号：US124923
申请日：1987-11-24
申请人： Keiji Kojima , Shunichi Torii , Akiharu Sakata
发明人： Keiji Kojima , Shunichi Torii , Akiharu Sakata
IPC分类号： G06F17/16 , G06F15/78
CPC分类号： G06F15/8053
摘要： A vector processor includes a memory for storing vector data, a processing circuit, a fetch circuit for sequentially fetching elements of a first vector data to be processed from the memory and supplying them to the processing circuit, a generation circuit for generating tag information to designate the fetched vector elements, and a write circuit responsive to the process result by the processing means for writing the tag information generated for the element having a predetermined process result into the memory as one element of a second vector data.
摘要翻译：矢量处理器包括用于存储矢量数据的存储器，处理电路，取出电路，用于从存储器中顺序提取要处理的第一矢量数据的元素并将其提供给处理电路;生成电路，用于产生标记信息以指定所取得的向量元素以及响应于处理装置的处理结果的写入电路，用于将为具有预定处理结果的元素生成的标签信息写入存储器作为第二向量数据的一个元素。

3. 发明授权

US5115392A Method and apparatus for multi-transaction batch processing 失效
标题翻译：多事务批处理方法和装置
公开(公告)号：US5115392A
公开(公告)日：1992-05-19
申请号：US106062
申请日：1987-10-07
申请人： Yoshifumi Takamoto , Shunichi Torii
发明人： Yoshifumi Takamoto , Shunichi Torii
IPC分类号： G06F15/00 , G06F9/46
CPC分类号： G06F9/466
摘要： In a data communication management system, a first transaction causes an application program to start. When a transaction arises, it is determined whether the transaction is to be batch processed as one of a plurality of transactions. Batch processing is determined based on the name of the transaction and the name of a application program requested. If it is determined that the transaction should not be batch processed, the transaction undergoes ordinary processing. If it is determined that the transaction is to be batch processed, the transaction is stored in a batch process queue. The application program for all transactions stored in the batch process queue is started when the number of transactions stored in the queue has exceeded a certain number or when a predetermined time length has elapsed after any transaction has been stored in the queue. After the application program is terminated, a batch synchronous point process is carried out for all the transactions. The transmission messages are then transmitted in batch fashion.
摘要翻译：在数据通信管理系统中，第一事务使应用程序启动。当交易出现时，确定交易是否被批处理为多个交易之一。批量处理是根据交易名称和所请求的应用程序的名称来确定的。如果确定交易不应该被批处理，则交易经历普通处理。如果确定事务要进行批处理，则事务将存储在批处理队列中。存储在批处理队列中的所有事务的应用程序在存储在队列中的事务数量已超过一定数量或者在任何事务已经存储在队列中之后经过预定时间长度时开始。应用程序终止后，对所有事务执行批处理同步点处理。然后以批量方式传输传输消息。

4. 发明授权

US07599910B1 Method and system of database divisional management for parallel database system 失效
标题翻译：并行数据库系统数据库分区管理方法与系统
公开(公告)号：US07599910B1
公开(公告)日：2009-10-06
申请号：US09665448
申请日：2000-09-19
申请人： Masashi Tsuchida , Kazuo Masai , Shunichi Torii
发明人： Masashi Tsuchida , Kazuo Masai , Shunichi Torii
IPC分类号： G06F17/30
CPC分类号： G06F9/5083 , G06F17/30584 , Y10S707/99932 , Y10S707/99933 , Y10S707/99936 , Y10S707/99953
摘要： A method and a system of database divisional management for use with a parallel database system comprising an FES (front end server), BES's (back end servers), an IOS (I/O server) and disk units. The numbers of processors assigned to the FES, BES's and IOS, the number of disk units, and the number of partitions of the disk units are determined in accordance with the load pattern in question. Illustratively, there may be established a configuration of one FES, four BES's, one IOS and eight disk units. The number of BES's is varied from one to four depending on the fluctuation in load, so that a scalable system configuration is implemented. When the number of BES's is increased or decreased, only the management information thereabout is transferred between nodes and not the data, whereby the desired degree of parallelism is obtained for high-speed query processing.
摘要翻译：一种与并行数据库系统一起使用的数据库分区管理方法和系统，包括FES（前端服务器），BES（后端服务器），IOS（I / O服务器）和磁盘单元。根据所讨论的负载模式确定分配给FES，BES和IOS的处理器的数量，磁盘单元的数量和磁盘单元的分区数。说明性地，可以建立一个FES，四个BES，一个IOS和八个磁盘单元的配置。根据负载波动，BES的数量从1到4不等，从而实现可扩展的系统配置。当BES的数量增加或减少时，仅在节点之间传送管理信息而不是数据，从而获得高速查询处理所需的并行度。

5. 发明授权

US06510428B2 Method and system of database divisional management for parallel database system 失效
公开(公告)号：US06510428B2
公开(公告)日：2003-01-21
申请号：US09805594
申请日：2001-03-14
申请人： Masashi Tsuchida , Kazuo Masai , Shunichi Torii
发明人： Masashi Tsuchida , Kazuo Masai , Shunichi Torii
IPC分类号： G06F1730
CPC分类号： G06F9/5083 , G06F17/30584 , Y10S707/99932 , Y10S707/99933 , Y10S707/99936 , Y10S707/99953
摘要： A method and a system of database divisional management for use with a parallel database system comprising an FES (front end server), BES's (back end servers), an IOS (I/O server) and disk units. The numbers of processors assigned to the FES, BES's and IOS, the number of disk units, and the number of partitions of the disk units are determined in accordance with the load pattern in question. Illustratively, there may be established a configuration of one FES, four BES's, one IOS and eight disk units. The number of BES's is varied from one to four depending on the fluctuation in load, so that a scalable system configuration is implemented. When the number of BES's is increased or decreased, only the management information thereabout is transferred between nodes and not the data, whereby the desired degree of parallelism is obtained for high-speed query processing.

6. 发明授权

US6003043A Text data registering and retrieving system including a database storing a plurality of document files therin and a plural-character occurrence table for a text index and an update text buffer to retrieve a target document in cooperation with the database 失效
标题翻译：文本数据注册和检索系统，包括存储文本索引的多个文档文件和多个字符出现表的数据库和更新文本缓冲器，以与数据库一起检索目标文档
公开(公告)号：US6003043A
公开(公告)日：1999-12-14
申请号：US956481
申请日：1997-10-23
申请人： Atsushi Hatakeyama , Shunichi Torii , Nobuo Kawamura , Yasushi Kawashimo
发明人： Atsushi Hatakeyama , Shunichi Torii , Nobuo Kawamura , Yasushi Kawashimo
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F17/30011 , Y10S707/99933 , Y10S707/99943 , Y10S707/99953 , Y10S707/99954
摘要： A text data registering and retrieving method capable of improving the transaction processing performance is provided. The document number of a document for which deletion or replacement has been newly requested is registered in an updated document number list. The text data of the document for which insertion or replacement has been newly requested is registered in an update text buffer. The text data stored temporarily in the update text buffer is registered in a plural-character occurrence file defining a text index in a character component file merge step. The data registered in the plural-character occurrence file is retrieved for query terms. The text data stored in the update text buffer is retrieved for the query terms. The document number of a document updated or deleted is deleted from the result of retrieval in the plural-character occurrence file. Also, the result or the document number obtained in the, update text buffer is added to the result of retrieval to provide a final retrieval result.
摘要翻译：提供了一种能够提高事务处理性能的文本数据注册和检索方法。更新的文件编号列表中登记了已经新请求删除或替换的文档的文档编号。已经新请求插入或替换的文档的文本数据被登记在更新文本缓冲器中。临时存储在更新文本缓冲器中的文本数据被登记在字符组件文件合并步骤中定义文本索引的多字符出现文件中。针对查询条件检索登记在多个字符出现文件中的数据。检索存储在更新文本缓冲区中的文本数据用于查询条件。更新或删除的文档的文档号从多字符出现文件中的检索结果中删除。此外，将更新文本缓冲器中获得的结果或文档编号添加到检索结果中以提供最终检索结果。

7. 发明授权

US5146599A System for fetching a plurality vector-data groups using a plurality of addressing device 失效
标题翻译：使用多个寻址装置取出多个矢量数据组的系统
公开(公告)号：US5146599A
公开(公告)日：1992-09-08
申请号：US489884
申请日：1990-03-07
申请人： Keiji Kojima , Shunichi Torii
发明人： Keiji Kojima , Shunichi Torii
IPC分类号： G06F17/16 , G06F15/78 , G06F17/30
CPC分类号： G06F15/8061 , G06F17/30958 , G06F17/30985
摘要： A data processor in which a plurality of address generator circuits corresponding to mutually different elements are provided for respective input vectors. Each address generator circuit updates an address upon waiting the arrival of data accessed by the address generator circuit. Also, access requests by respective address generator circuits are issued with a shift of one clock between an adjacent request. Therefore an access request is issued for data every cycle so as to completely fill each cycle of the complete process.
摘要翻译：一种数据处理器，其中为相应的输入向量提供对应于相互不同的元素的多个地址发生器电路。每个地址发生器电路在等待由地址发生器电路访问的数据到达时更新地址。而且，相应地址发生器电路的访问请求被发出，在相邻请求之间移动一个时钟。因此，每个周期为数据发出访问请求，以便完全填满整个过程的每个周期。

8. 发明授权

US5109523A Method for determining whether data signals of a first set are related to data signal of a second set 失效
标题翻译：用于确定第一组的数据信号是否与第二组的数据信号相关的方法
公开(公告)号：US5109523A
公开(公告)日：1992-04-28
申请号：US481706
申请日：1990-02-15
申请人： Yasusi Kanada , Shunichi Torii , Keiji Kojima
发明人： Yasusi Kanada , Shunichi Torii , Keiji Kojima
IPC分类号： G06F9/44
CPC分类号： G06F9/4438
摘要： A method for controlling a vector processor so as to detect whether or not a value of each data signal among a first set of data signals has a specific relation with a value of one of a second set of data signals. The vector processor includes an operation unit for performing an arithmetical or logical operation in a pipeline manner on vector data. First and second vector data are formed each including groups of data signals related to the first and second set of data signals. The operation of the operation unit is controlled such that the operation unit detects whether or not a value of each data signal of the first vector data has a specific relation with a value of a corresponding data signal of the second vector data. Third vector data including result data signals is generated thereby which indicate the result of the operation.
摘要翻译：一种用于控制矢量处理器以便检测第一组数据信号中的每个数据信号的值是否与第二组数据信号之一具有特定关系的方法。矢量处理器包括用于以流水线方式对矢量数据执行算术或逻辑运算的操作单元。形成第一和第二矢量数据，每个包括与第一和第二组数据信号有关的数据信号组。控制操作单元的操作使得操作单元检测第一矢量数据的每个数据信号的值是否与第二矢量数据的相应数据信号的值具有特定关系。产生包括结果数据信号的第三矢量数据，由此指示操作的结果。

9. 发明授权

US4734850A Data process system including plural storage means each capable of concurrent and intermediate reading and writing of a set of data signals 失效
标题翻译：数据处理系统包括多个存储装置，每个存储装置能够并行和中间读取和写入一组数据信号
公开(公告)号：US4734850A
公开(公告)日：1988-03-29
申请号：US581077
申请日：1984-02-17
申请人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
发明人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
IPC分类号： G06F3/06 , G06F5/06 , G06F5/16 , G06F12/00 , G06F12/06 , G06F17/16 , G11C7/00 , G06F9/18
CPC分类号： G06F5/16
摘要： A data processing system having a plurality of FIFO memories and a plurality of ALUs and in which a FIFO memory may be selected to receive a set of data signals from an ALU and at the same time to be selected to provide a set of data signals to another ALU, with the result that the selected FIFO memory performs read and write operations concurrently and intermittently. Also, a set of data signals held by one of the FIFO memories may be transferred to a selected ALU for effecting a logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation by the selected ALU may be transferred to another FIFO memory.
摘要翻译：一种具有多个FIFO存储器和多个ALU的数据处理系统，其中可以选择FIFO存储器以从ALU接收一组数据信号，并且同时被选择以提供一组数据信号另一个ALU，结果是所选择的FIFO存储器同时并间歇地执行读写操作。此外，由FIFO存储器中的一个保存的一组数据信号可以被传送到所选择的ALU以进行其上的逻辑或算术运算，并且表示其上的逻辑或运算结果的结果的数据信号，以及代表所选择的ALU的逻辑或算术运算的结果可以被传送到另一个FIFO存储器。

10. 发明授权

US4441152A Data processing system having ring-like connected multiprocessors relative to key storage 失效
标题翻译：数据处理系统相对于密钥存储具有环状连接的多处理器
公开(公告)号：US4441152A
公开(公告)日：1984-04-03
申请号：US233447
申请日：1981-02-11
申请人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
发明人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
IPC分类号： G06F12/00 , G06F9/46 , G06F12/14 , G06F15/16 , G06F15/177 , G06F13/00
CPC分类号： G06F9/52 , G06F12/1466 , G06F15/16
摘要： A multiprocessor system includes a plurality of central processing units (CPUs), which have a main storage in common, and a key storage for storing therein control information for storage protection of, reference to, and change in the main storage. Each CPU is provided with the key storage, the CPUs are connected by interface lines so as to form a ring-like combination, a CPU in which a key access request is generated, carries out the key processing for its own key storage and supplies the interface line with an address, data and others which are contained in the key access request, and another CPU receives the address, data and others to perform the key processing for its own key storage. A signal for determining the priority among key access requests simultaneously generated in a plurality of central processing units circulates through the CPUs via the interface lines, one of the CPUs having generated the key access requests catches the priority determining signal to make its own key access request valid, and prevents the circulation of the priority determining signal for a time till the key processing based upon the valid request has been completed.
摘要翻译：多处理器系统包括具有共同的主存储器的多个中央处理单元（CPU）和用于存储用于主存储器的存储保护，参考和变化的控制信息的密钥存储器。每个CPU都配有密钥存储器，CPU通过接口线连接，形成环状组合，生成密钥访问请求的CPU执行自身密钥存储的密钥处理，并提供接口线，其包含在密钥访问请求中的地址，数据等，另一个CPU接收地址，数据等，以对其自己的密钥存储进行密钥处理。用于确定在多个中央处理单元中同时产生的密钥访问请求中的优先级的信号经由接口线通过CPU循环，生成密钥访问请求的一个CPU捕获优先级确定信号以使其自己的密钥访问请求有效，并且防止优先级确定信号的循环一段时间，直到基于有效请求的密钥处理已经完成。

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