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1. 发明授权

US06636064B1 Dual probe test structures for semiconductor integrated circuits 有权
标题翻译：半导体集成电路的双探针测试结构
公开(公告)号：US06636064B1
公开(公告)日：2003-10-21
申请号：US09648092
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Neil Richardson , Kurt H. Weiner , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Neil Richardson , Kurt H. Weiner , David J. Walker
IPC分类号： G01R3128
CPC分类号： H01L22/34 , G01N21/66 , G01N21/9501 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.
摘要翻译：公开了具有上层和下层的半导体管芯。模具包括形成在半导体管芯的下金属层中的下部测试结构。下导电测试结构具有第一端和第二端，其中第一端耦合到预定的电压电平。模具还具有形成在下金属层上的绝缘层和形成在半导体管芯的上金属层中的上测试结构。上导电测试结构与下导电测试结构的第二端耦合，并且上金属层形成在绝缘层上。芯片还包括与上测试结构耦合的至少一个探针焊盘。优选地，下测试结构的第一端耦合到标称接地电位。在另一实施方案中，上测试结构是电压对比元件。在另一实施例中，公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。模具包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分地位于扫描区域内。第一多个测试结构或第二多个测试结构具有耦合到至少一个测试结构的探针焊盘。

2. 发明授权

US06528818B1 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06528818B1
公开(公告)日：2003-03-04
申请号：US09648380
申请日：2000-08-25
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： H01L2358
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

3. 发明授权

US06921672B2 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06921672B2
公开(公告)日：2005-07-26
申请号：US10338936
申请日：2003-01-07
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： G01N21/66 , G01N21/95 , G01N21/956 , G01R31/28 , G01R31/307 , H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

4. 发明授权

US06633174B1 Stepper type test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：步进式测试结构和半导体集成电路检测方法
公开(公告)号：US06633174B1
公开(公告)日：2003-10-14
申请号：US09648093
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Neil Richardson , Gustavo A. Pinto , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Neil Richardson , Gustavo A. Pinto , David J. Walker
IPC分类号： G01R31305
CPC分类号： G01R31/307 , G01N21/66 , G01N21/9501 , G01N21/956 , G01R31/2884 , H01J2237/2817 , H01L22/12 , H01L22/34 , Y10S977/85 , Y10S977/86 , Y10S977/881
摘要： Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.
摘要翻译：公开了一种检查样品的方法。该方法包括移动到与第一组测试结构相关联的第一字段。第一组测试结构部分在第一个领域内。该方法还包括扫描第一场以确定在第一组测试结构内是否存在任何缺陷。当确定在第一组测试结构内存在缺陷时，该方法还包括重复地步进到区域并扫描这些区域，以便确定第一组测试结构内的特定缺陷位置。还公开了用于执行该方法的合适的测试结构。

5. 发明授权

US06524873B1 Continuous movement scans of test structures on semiconductor integrated circuits 有权
标题翻译：半导体集成电路测试结构的连续运动扫描
公开(公告)号：US06524873B1
公开(公告)日：2003-02-25
申请号：US09648094
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Bin-Ming Benjamin Tsai , Neil Richardson , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Bin-Ming Benjamin Tsai , Neil Richardson , David J. Walker
IPC分类号： G01R3126
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.
摘要翻译：公开了一种用于检测半导体管芯的测试结构上的电缺陷的方法。半导体管芯包括多个电绝缘测试结构和多个非电隔离测试结构。为多个电隔离测试结构建立电压。这些电压不同于多个非电隔离测试结构的电压。在第一方向上连续地检查半导体管芯的区域，从而获得表示是否存在缺陷的测试结构的电压对比度数据。分析电压对比度数据以确定是否存在一个或多个有缺陷的测试结构。

6. 发明申请

US20080246030A1 TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS 审中-公开
标题翻译：用于检查半导体集成电路的测试结构和方法
公开(公告)号：US20080246030A1
公开(公告)日：2008-10-09
申请号：US11675021
申请日：2007-02-14
申请人： Akella V.S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas , Padma A. Satya
发明人： Akella V.S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas , Padma A. Satya
IPC分类号： H01L23/58 , H01L21/00
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

7. 发明授权

US06771806B1 Multi-pixel methods and apparatus for analysis of defect information from test structures on semiconductor devices 有权
标题翻译：用于分析半导体器件上测试结构的缺陷信息的多像素方法和装置
公开(公告)号：US06771806B1
公开(公告)日：2004-08-03
申请号：US09648381
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Bin-Ming Benjamin Tsai , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Bin-Ming Benjamin Tsai , David J. Walker
IPC分类号： G06K900
CPC分类号： H01L22/34 , G01N21/66 , G01N21/9501 , G01N21/956 , G01R31/2884 , G01R31/307
摘要： Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure's line width to maximize throughput at optimal signal to noise sensitivity. A computer readable medium having programming instructions for performing the above described methods is also disclosed.
摘要翻译：公开了一种用于检测半导体管芯的测试结构上的电缺陷的方法。测试结构包括多个电隔离测试结构和多个非电隔离测试结构。测试结构各自具有部分位于扫描区域内的部分。扫描区域内的测试结构部分被扫描，以获得测试结构部分的电压对比度图像。在多像素处理器中，分析获得的电压对比图像，以确定测试结构内是否存在缺陷。在优选实施例中，多像素处理器以约25nm至200nm的范围内的像素分辨率尺寸进行操作。在另一方面，处理器以标称等于测试结构线宽度的两倍的像素大小进行操作，以在最佳信噪比灵敏度下最大化吞吐量。还公开了一种具有用于执行上述方法的编程指令的计算机可读介质。

8. 发明授权

US06566885B1 Multiple directional scans of test structures on semiconductor integrated circuits 有权
标题翻译：半导体集成电路测试结构的多方向扫描
公开(公告)号：US06566885B1
公开(公告)日：2003-05-20
申请号：US09648109
申请日：2000-08-25
申请人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
发明人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
IPC分类号： G01R3100
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01N23/04 , G01R31/2884 , G01R31/307 , H01J2237/2817 , Y10S977/849
摘要： A sample is inspected. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.
摘要翻译：检查样品。用至少一个粒子束沿第一方向扫描样品。用至少一个粒子束在第二个方向上扫描样品。第二方向与第一方向成一个角度。作为第一扫描的结果，发现样品的每个区域的缺陷数，并且从第二次扫描确定发现的一个或多个缺陷的位置。在具体实施例中，样本包括其上具有多个测试元件的测试结构。测试元件的第一部分在第一次扫描期间暴露于光束以识别具有缺陷的测试元件，并且第二部分测试元件在第二次扫描期间暴露以分离和表征缺陷。

9. 发明授权

US07656170B2 Multiple directional scans of test structures on semiconductor integrated circuits 有权
标题翻译：半导体集成电路测试结构的多方向扫描
公开(公告)号：US07656170B2
公开(公告)日：2010-02-02
申请号：US11675013
申请日：2007-02-14
申请人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Padma A. Satya, legal representative , Robert Thomas Long , David J. Walker
发明人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
IPC分类号： G01R31/02
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.
摘要翻译：公开了一种检查样品的方法。用至少一个粒子束沿第一方向扫描样品。用至少一个粒子束在第二个方向上扫描样品。第二方向与第一方向成一个角度。作为第一扫描的结果，发现样品的每个区域的缺陷数，并且从第二次扫描确定发现的一个或多个缺陷的位置。在具体实施例中，样本包括其上具有多个测试元件的测试结构。测试元件的第一部分在第一次扫描期间暴露于光束以识别具有缺陷的测试元件，并且第二部分测试元件在第二次扫描期间暴露以分离和表征缺陷。

10. 发明授权

US06867606B2 Multiple directional scans of test structures on semiconductor integrated circuits 有权
公开(公告)号：US06867606B2
公开(公告)日：2005-03-15
申请号：US10390502
申请日：2003-03-13
申请人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
发明人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
IPC分类号： G01N21/66 , G01N21/95 , G01N21/956 , G01N23/04 , G01Q30/16 , G01Q60/44 , G01R31/28 , G01R31/307 , H01L23/544 , G01R31/304
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01N23/04 , G01R31/2884 , G01R31/307 , H01J2237/2817 , Y10S977/849
摘要： Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

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