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1. 发明授权

US06524873B1 Continuous movement scans of test structures on semiconductor integrated circuits 有权
标题翻译：半导体集成电路测试结构的连续运动扫描
公开(公告)号：US06524873B1
公开(公告)日：2003-02-25
申请号：US09648094
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Bin-Ming Benjamin Tsai , Neil Richardson , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Bin-Ming Benjamin Tsai , Neil Richardson , David J. Walker
IPC分类号： G01R3126
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.
摘要翻译：公开了一种用于检测半导体管芯的测试结构上的电缺陷的方法。半导体管芯包括多个电绝缘测试结构和多个非电隔离测试结构。为多个电隔离测试结构建立电压。这些电压不同于多个非电隔离测试结构的电压。在第一方向上连续地检查半导体管芯的区域，从而获得表示是否存在缺陷的测试结构的电压对比度数据。分析电压对比度数据以确定是否存在一个或多个有缺陷的测试结构。

2. 发明授权

US06636064B1 Dual probe test structures for semiconductor integrated circuits 有权
标题翻译：半导体集成电路的双探针测试结构
公开(公告)号：US06636064B1
公开(公告)日：2003-10-21
申请号：US09648092
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Neil Richardson , Kurt H. Weiner , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Neil Richardson , Kurt H. Weiner , David J. Walker
IPC分类号： G01R3128
CPC分类号： H01L22/34 , G01N21/66 , G01N21/9501 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.
摘要翻译：公开了具有上层和下层的半导体管芯。模具包括形成在半导体管芯的下金属层中的下部测试结构。下导电测试结构具有第一端和第二端，其中第一端耦合到预定的电压电平。模具还具有形成在下金属层上的绝缘层和形成在半导体管芯的上金属层中的上测试结构。上导电测试结构与下导电测试结构的第二端耦合，并且上金属层形成在绝缘层上。芯片还包括与上测试结构耦合的至少一个探针焊盘。优选地，下测试结构的第一端耦合到标称接地电位。在另一实施方案中，上测试结构是电压对比元件。在另一实施例中，公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。模具包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分地位于扫描区域内。第一多个测试结构或第二多个测试结构具有耦合到至少一个测试结构的探针焊盘。

3. 发明授权

US06921672B2 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06921672B2
公开(公告)日：2005-07-26
申请号：US10338936
申请日：2003-01-07
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： G01N21/66 , G01N21/95 , G01N21/956 , G01R31/28 , G01R31/307 , H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

4. 发明授权

US06528818B1 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06528818B1
公开(公告)日：2003-03-04
申请号：US09648380
申请日：2000-08-25
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： H01L2358
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

5. 发明授权

US06633174B1 Stepper type test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：步进式测试结构和半导体集成电路检测方法
公开(公告)号：US06633174B1
公开(公告)日：2003-10-14
申请号：US09648093
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Neil Richardson , Gustavo A. Pinto , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Neil Richardson , Gustavo A. Pinto , David J. Walker
IPC分类号： G01R31305
CPC分类号： G01R31/307 , G01N21/66 , G01N21/9501 , G01N21/956 , G01R31/2884 , H01J2237/2817 , H01L22/12 , H01L22/34 , Y10S977/85 , Y10S977/86 , Y10S977/881
摘要： Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.
摘要翻译：公开了一种检查样品的方法。该方法包括移动到与第一组测试结构相关联的第一字段。第一组测试结构部分在第一个领域内。该方法还包括扫描第一场以确定在第一组测试结构内是否存在任何缺陷。当确定在第一组测试结构内存在缺陷时，该方法还包括重复地步进到区域并扫描这些区域，以便确定第一组测试结构内的特定缺陷位置。还公开了用于执行该方法的合适的测试结构。

6. 发明授权

US06445199B1 Methods and apparatus for generating spatially resolved voltage contrast maps of semiconductor test structures 有权
标题翻译：用于生成半导体测试结构的空间分辨电压对比图的方法和装置
公开(公告)号：US06445199B1
公开(公告)日：2002-09-03
申请号：US09648379
申请日：2000-08-25
申请人： Akella V. S. Satya , Brian C. Leslie , Gustavo A. Pinto , Robert Thomas Long , Neil Richardson , Bin-Ming Benjamin Tsai
发明人： Akella V. S. Satya , Brian C. Leslie , Gustavo A. Pinto , Robert Thomas Long , Neil Richardson , Bin-Ming Benjamin Tsai
IPC分类号： G01R31308
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a method of inspecting a sample. The sample is illuminated with an incident beam, thereby causing voltage contrast within structures present on the sample. Voltage contrast is detected within the structures. Information from the detected voltage contrast is stored, and position data concerning the location of features corresponding to at least a portion of the stored voltage contrast information is also stored. In a specific embodiment, the features represent electrical defects present on the sample. In another embodiment, the stored position data is in the form of a two dimensional map. In another aspect, the sample is re-inspected and the stored position data is used in analyzing data resulting from the re-inspection.
摘要翻译：公开了一种检查样品的方法。样品用入射光照射，从而在样品中存在的结构内引起电压对比。在结构内检测到电压对比度。存储来自检测到的电压对比度的信息，并且还存储与存储的电压对比度信息的至少一部分相对应的特征位置的位置数据。在具体实施例中，特征表示样品上存在的电缺陷。在另一个实施例中，存储的位置数据是二维地图的形式。在另一方面，重新检查样本，并且将存储的位置数据用于分析由重新检查产生的数据。

7. 发明授权

US06576923B2 Inspectable buried test structures and methods for inspecting the same 有权
公开(公告)号：US06576923B2
公开(公告)日：2003-06-10
申请号：US10178329
申请日：2002-06-21
申请人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
发明人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
IPC分类号： H01L2358
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S977/712 , Y10S977/723 , Y10S977/888 , Y10S977/89 , H01L2924/00
摘要： Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

8. 发明授权

US06509197B1 Inspectable buried test structures and methods for inspecting the same 有权
公开(公告)号：US06509197B1
公开(公告)日：2003-01-21
申请号：US09648212
申请日：2000-08-25
申请人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
发明人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
IPC分类号： H01L2100
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

9. 发明申请

US20080246030A1 TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS 审中-公开
标题翻译：用于检查半导体集成电路的测试结构和方法
公开(公告)号：US20080246030A1
公开(公告)日：2008-10-09
申请号：US11675021
申请日：2007-02-14
申请人： Akella V.S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas , Padma A. Satya
发明人： Akella V.S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas , Padma A. Satya
IPC分类号： H01L23/58 , H01L21/00
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

10. 发明授权

US5869833A Electron beam dose control for scanning electron microscopy and critical dimension measurement instruments 失效
标题翻译：扫描电子显微镜和关键尺寸测量仪器的电子束剂量控制
公开(公告)号：US5869833A
公开(公告)日：1999-02-09
申请号：US784749
申请日：1997-01-16
申请人： Neil Richardson , Farid Askary , Stefano E. Concina , Kevin M. Monahan , David L. Adler
发明人： Neil Richardson , Farid Askary , Stefano E. Concina , Kevin M. Monahan , David L. Adler
IPC分类号： H01J37/20 , H01J37/147 , H01J37/28 , H01J37/00
CPC分类号： H01J37/28 , H01J2237/004 , H01J2237/2817
摘要： A system and method for controlling electron exposure on image specimens by adjusting a raster scan area in-between scan frame cycles. A small, zoomed-in, scan area and the surrounding area are flooded with positive charge for a number of frame cycles between scan frames to reduce the voltage differential between the scan area and surrounding area, thereby reducing the positive charge buildup which tends to obscure small features in scanned images. The peak current into a pixel element on the specimen is reduced by scanning the beam with a line period that is very short compared to regular video. Frames of image data may further be acquired non-sequentially, in arbitrarily programmable patterns. Alternatively, an inert gas can be injected into the scanning electron microscope at the point where the electron beam impinges the specimen to neutralize a charge build-up on the specimen by the ionization of the inert gas by the electron beam.
摘要翻译：通过调整扫描帧周期之间的光栅扫描区域来控制图像样本上的电子曝光的系统和方法。一个小的，放大的扫描区域和周围区域在扫描帧之间的多个帧周期中充满正电荷，以减少扫描区域和周围区域之间的电压差，从而减少倾向于模糊的正电荷积聚扫描图像中的小功能。通过以与常规视频相比非常短的线周期扫描光束来减小进入样品中的像素元件的峰值电流。图像数据的帧可以以任意可编程的模式进一步非依次获取。或者，可以在电子束照射样品的点处将惰性气体注入到扫描电子显微镜中，以通过电子束电离惰性气体来中和样品上的电荷积累。

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