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1. 发明授权

US5985680A Method and apparatus for transforming a substrate coordinate system into a wafer analysis tool coordinate system 失效
标题翻译：将基板坐标系转换成晶片分析工具坐标系的方法和装置
公开(公告)号：US5985680A
公开(公告)日：1999-11-16
申请号：US907590
申请日：1997-08-08
申请人： Ajay Singhal , Yuri Uritsky , Patrick D. Kinney
发明人： Ajay Singhal , Yuri Uritsky , Patrick D. Kinney
IPC分类号： G01N21/94 , G03F7/20 , G03F9/00 , H01L21/00
CPC分类号： H01L21/67288 , G01N21/94 , G03F7/7065 , G03F9/70
摘要： A method and apparatus for accurately transforming coordinates within a first coordinate system (e.g., a two-dimensional coordinate system associated with a substrate (or portion thereof)) into coordinates in a second coordinate system (e.g., a three-dimensional coordinate system of substrate (or portion thereof) tilted within a wafer analysis tool.
摘要翻译：一种用于将第一坐标系（例如，与衬底（或其部分）相关联的二维坐标系）中的坐标精确地变换为第二坐标系（例如，衬底的三维坐标系）的坐标的方法和装置（或其部分）在晶片分析工具内倾斜。

2. 发明授权

US6122562A Method and apparatus for selectively marking a semiconductor wafer 失效
标题翻译：用于选择性地标记半导体晶片的方法和装置
公开(公告)号：US6122562A
公开(公告)日：2000-09-19
申请号：US850954
申请日：1997-05-05
申请人： Patrick D. Kinney , Yuri Uritsky , Nagaraja Rao
发明人： Patrick D. Kinney , Yuri Uritsky , Nagaraja Rao
IPC分类号： H01L21/66 , G01Q30/02 , G01Q30/04 , G01Q60/00 , G01Q80/00 , G01Q90/00 , H01L21/00 , H01L21/02 , G06F19/00
CPC分类号： H01L21/67282
摘要： A method and apparatus that accurately marks a wafer at selected locations such as a defect location on the surface of a wafer such that a wafer analysis system (e.g., SEM or AFM) may rapidly find the defect. The apparatus contains a wafer platen for retaining a wafer in a substantially horizontal orientation and a marking assembly mounted above the wafer platen. The marking assembly further contains an optical microscope and a marking head. In operation, a user locates a defect using the optical microscope and places a pattern of fiducial marks at a predetermined distance from the defect, e.g., four marks in a diamond pattern circumscribing the defect.
摘要翻译：精确地将晶片标记在晶片表面上的缺陷位置等选定位置的方法和装置，使得晶片分析系统（例如，SEM或AFM）可以快速找到缺陷。该装置包括用于将晶片保持在基本水平的方向的晶片台板和安装在晶片台板上方的标记组件。标记组件还包含光学显微镜和标记头。在操作中，用户使用光学显微镜来定位缺陷，并将基准标记的图案放置在距离缺陷的预定距离处，例如限定在缺陷处的菱形图案中的四个标记。

3. 发明授权

US5870187A Method for aligning semiconductor wafer surface scans and identifying added and removed particles resulting from wafer handling or processing 失效
标题翻译：用于对准半导体晶片表面扫描并识别由晶片处理或加工产生的添加和去除的颗粒的方法
公开(公告)号：US5870187A
公开(公告)日：1999-02-09
申请号：US907589
申请日：1997-08-08
申请人： Yuri Uritsky , Patrick D. Kinney , Man-Ping Cai
发明人： Yuri Uritsky , Patrick D. Kinney , Man-Ping Cai
IPC分类号： G01N21/95 , G01N21/00
CPC分类号： G01N21/9501
摘要： An automated method for aligning wafer surface scan maps and locating defects such as particle contaminant distributions on a wafer surface. More specifically, the invention is an automated method for locating added and removed contaminants and other defects on a semiconductor wafer surface after the wafer has undergone wafer-handling and/or processing. A second data set of a second scan of a wafer surface is misalignment-corrected to a first coordinate system of a first scan of the wafer surface. Thereafter, a final match is made between a first data set of the first scan and the misalignment-corrected data of the second scan. Non-matching locations in the misalignment-corrected data of the second scan represent added defects on the surface of the wafer. Non-matching locations in the base data of the first scan represent removed defects from the surface of the wafer.
摘要翻译：用于对准晶片表面扫描图并定位诸如颗粒污染物分布在晶片表面上的缺陷的自动化方法。更具体地，本发明是一种自动化方法，用于在晶片经过晶片处理和/或处理之后，在半导体晶片表面上定位添加和去除的污染物和其它缺陷。晶片表面的第二次扫描的第二数据组对于晶片表面的第一次扫描的第一坐标系进行未对准校正。此后，在第一扫描的第一数据集和第二扫描的未对准校正数据之间进行最终匹配。第二扫描的未对准校正数据中的非匹配位置表示晶片表面上的附加缺陷。第一次扫描的基础数据中的非匹配位置表示从晶片表面去除的缺陷。

4. 发明授权

US07601648B2 Method for fabricating an integrated gate dielectric layer for field effect transistors 有权
标题翻译：用于制造用于场效应晶体管的集成栅介质层的方法
公开(公告)号：US07601648B2
公开(公告)日：2009-10-13
申请号：US11496411
申请日：2006-07-31
申请人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
发明人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , H01L21/02046 , H01L21/02052 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/0228 , H01L21/02315 , H01L21/02337 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/31662 , H01L21/3185 , H01L29/513
摘要： Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.
摘要翻译：提供了在基板上形成集成栅电介质层的方法。在一个实施例中，该方法包括在衬底上形成氧化硅层，等离子体处理氧化硅层，通过ALD工艺在氧化硅层上沉积氮化硅层，以及对衬底进行热退火。在另一个实施例中，该方法包括预先清洗衬底，在衬底上形成氧化硅层，等离子体处理氧化硅层，通过ALD工艺在氧化硅层上沉积氮化硅层，以及对衬底进行热退火，其中形成的氧化硅层，并且氮化硅层的总厚度小于作为栅极结构中的栅极介电层的厚度。

5. 发明授权

US5474640A Apparatus for marking a substrate using ionized gas 失效
标题翻译：用于使用电离气体标记基板的设备
公开(公告)号：US5474640A
公开(公告)日：1995-12-12
申请号：US94653
申请日：1993-07-19
申请人： Yan Ye , Anand Gupta , Yuri Uritsky
发明人： Yan Ye , Anand Gupta , Yuri Uritsky
IPC分类号： H01L21/68 , H01J37/304 , H01L21/00 , H01L21/02 , H01L23/544 , C23F1/02
CPC分类号： H01L21/67282 , H01J37/3045 , H01L23/544 , H01L2223/54453 , H01L2924/0002
摘要： An apparatus suitable for marking a substrate comprises a holder for holding a substrate and a ground for electrically grounding the substrate. At least one needle electrode has a tip located proximate to the substrate so that there is a gap between the substrate and the tip. A high voltage source provides a current to the electrode tip to ionize the gas in the gap so that the ionized gas can impinge upon and mark the substrate.
摘要翻译：适用于标记衬底的装置包括用于保持衬底的保持器和用于使衬底电接地的接地。至少一个针电极具有位于基底附近的尖端，使得在基底和尖端之间存在间隙。高电压源向电极尖端提供电流以离子化间隙中的气体，使得电离气体可以撞击并标记衬底。

6. 发明授权

US6051845A Method and apparatus for selectively marking a semiconductor wafer 失效
标题翻译：用于选择性地标记半导体晶片的方法和装置
公开(公告)号：US6051845A
公开(公告)日：2000-04-18
申请号：US48235
申请日：1998-03-25
申请人： Yuri Uritsky
发明人： Yuri Uritsky
IPC分类号： H01L21/00 , G01N21/86
CPC分类号： H01L21/67282 , H01L2223/54493
摘要： A method and apparatus that accurately marks a wafer at selected locations to form a wafer coordinate system. The apparatus contains a wafer platen for retaining a wafer in a substantially horizontal orientation, a wafer orientation detector assembly and a marking assembly mounted above the wafer platen. In operation, the apparatus orients the wafer by identifying an orientation attribute of the wafer, then applies fiducial marks to the wafer. The wafer marking apparatus forms a portion of an integrated analytical tool.
摘要翻译：一种在选定位置精确地标记晶片以形成晶片坐标系的方法和装置。该装置包含用于将晶片保持在基本水平取向的晶片台板，晶片定向检测器组件和安装在晶片台板上方的标记组件。在操作中，该装置通过识别晶片的取向属性来定向晶片，然后对晶片施加基准标记。晶片标记装置形成一体化分析工具的一部分。

7. 发明申请

US20080026553A1 Method for fabricating an integrated gate dielectric layer for field effect transistors 有权
标题翻译：用于制造用于场效应晶体管的集成栅介质层的方法
公开(公告)号：US20080026553A1
公开(公告)日：2008-01-31
申请号：US11496411
申请日：2006-07-31
申请人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
发明人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/3105 , H01L21/02046 , H01L21/02052 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/0228 , H01L21/02315 , H01L21/02337 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/31662 , H01L21/3185 , H01L29/513
摘要： Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.
摘要翻译：提供了在基板上形成集成栅电介质层的方法。在一个实施例中，该方法包括在衬底上形成氧化硅层，等离子体处理氧化硅层，通过ALD工艺在氧化硅层上沉积氮化硅层，以及对衬底进行热退火。在另一个实施例中，该方法包括预先清洗衬底，在衬底上形成氧化硅层，等离子体处理氧化硅层，通过ALD工艺在氧化硅层上沉积氮化硅层，以及对衬底进行热退火，其中形成的氧化硅层，并且氮化硅层的总厚度小于作为栅极结构中的栅极介电层的厚度。

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