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1. 发明授权

US07601648B2 Method for fabricating an integrated gate dielectric layer for field effect transistors 有权
标题翻译：用于制造用于场效应晶体管的集成栅介质层的方法
公开(公告)号：US07601648B2
公开(公告)日：2009-10-13
申请号：US11496411
申请日：2006-07-31
申请人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
发明人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , H01L21/02046 , H01L21/02052 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/0228 , H01L21/02315 , H01L21/02337 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/31662 , H01L21/3185 , H01L29/513
摘要： Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.
摘要翻译：提供了在基板上形成集成栅电介质层的方法。在一个实施例中，该方法包括在衬底上形成氧化硅层，等离子体处理氧化硅层，通过ALD工艺在氧化硅层上沉积氮化硅层，以及对衬底进行热退火。在另一个实施例中，该方法包括预先清洗衬底，在衬底上形成氧化硅层，等离子体处理氧化硅层，通过ALD工艺在氧化硅层上沉积氮化硅层，以及对衬底进行热退火，其中形成的氧化硅层，并且氮化硅层的总厚度小于作为栅极结构中的栅极介电层的厚度。

2. 发明申请

US20080026553A1 Method for fabricating an integrated gate dielectric layer for field effect transistors 有权
标题翻译：用于制造用于场效应晶体管的集成栅介质层的方法
公开(公告)号：US20080026553A1
公开(公告)日：2008-01-31
申请号：US11496411
申请日：2006-07-31
申请人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
发明人： Thai Cheng Chua , Shankar Muthukrisnan , Johanes Swenberg , Shreyas Kher , Chikuang Charles Wang , Giuseppina Conti , Yuri Uritsky
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/3105 , H01L21/02046 , H01L21/02052 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/0228 , H01L21/02315 , H01L21/02337 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/31662 , H01L21/3185 , H01L29/513
摘要： Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.
摘要翻译：提供了在基板上形成集成栅电介质层的方法。在一个实施例中，该方法包括在衬底上形成氧化硅层，等离子体处理氧化硅层，通过ALD工艺在氧化硅层上沉积氮化硅层，以及对衬底进行热退火。在另一个实施例中，该方法包括预先清洗衬底，在衬底上形成氧化硅层，等离子体处理氧化硅层，通过ALD工艺在氧化硅层上沉积氮化硅层，以及对衬底进行热退火，其中形成的氧化硅层，并且氮化硅层的总厚度小于作为栅极结构中的栅极介电层的厚度。

3. 发明申请

US20070049043A1 Nitrogen profile engineering in HI-K nitridation for device performance enhancement and reliability improvement 审中-公开
标题翻译：氮化硅工程在HI-K氮化中的设备性能提升和可靠性提高
公开(公告)号：US20070049043A1
公开(公告)日：2007-03-01
申请号：US11209472
申请日：2005-08-23
申请人： Shankar Muthukrishnan , Rahul Sharangpani , Tejal Goyani , Pravin Narwankar , Shreyas Kher , Yi Ma , Giuseppina Conti
发明人： Shankar Muthukrishnan , Rahul Sharangpani , Tejal Goyani , Pravin Narwankar , Shreyas Kher , Yi Ma , Giuseppina Conti
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , H01L21/02329 , H01L21/28202 , H01L21/3144 , H01L21/3145 , H01L21/31645 , H01L29/517
摘要： A method and apparatus for forming a nitrided gate dielectric. The method comprises incorporating nitrogen into a dielectric film using a plasma nitridation process to form a nitrided gate dielectric. The first step involves providing a substrate comprising a gate dielectric film. The second step involves inducing a voltage on the substrate. Finally, the substrate is exposed to a plasma comprising a nitrogen source while maintaining the voltage to form a nitrided gate dielectric on the substrate. In one embodiment, the voltage is induced on the substrate by applying a voltage to an electrostatic chuck supporting the substrate. In another embodiment, the voltage is induced on the substrate by applying a DC bias voltage to an electrode positioned adjacent the substrate.
摘要翻译：一种用于形成氮化栅极电介质的方法和装置。该方法包括使用等离子体氮化工艺将氮合并到电介质膜中以形成氮化栅极电介质。第一步涉及提供包括栅介质膜的衬底。第二步涉及在衬底上感应电压。最后，将衬底暴露于包含氮源的等离子体，同时保持电压以在衬底上形成氮化栅电介质。在一个实施例中，通过向支撑衬底的静电卡盘施加电压来在衬底上感应电压。在另一个实施例中，通过对邻近衬底定位的电极施加DC偏置电压来在衬底上感应出电压。

4. 发明授权

US08343279B2 Apparatuses for atomic layer deposition 有权
标题翻译：用于原子层沉积的装置
公开(公告)号：US08343279B2
公开(公告)日：2013-01-01
申请号：US11127753
申请日：2005-05-12
申请人： Nyi Oo Myo , Kenric Choi , Shreyas Kher , Pravin Narwankar , Steve Poppe , Craig R. Metzner , Paul Deaten
发明人： Nyi Oo Myo , Kenric Choi , Shreyas Kher , Pravin Narwankar , Steve Poppe , Craig R. Metzner , Paul Deaten
IPC分类号： C23C16/00
CPC分类号： C23C16/4488 , C23C16/0272 , C23C16/40 , C23C16/401 , C23C16/405 , C23C16/4412 , C23C16/45529 , C23C16/45531 , C23C16/45544 , C23C16/45582 , C23C16/56 , Y02T50/67 , Y10T137/0357 , Y10T137/0396 , Y10T137/2087
摘要： Embodiments of the invention provide apparatuses and methods for depositing materials on substrates during vapor deposition processes, such as atomic layer deposition (ALD). In one embodiment, a chamber contains a substrate support with a receiving surface and a chamber lid containing an expanding channel formed within a thermally insulating material. The chamber further includes at least one conduit coupled to a gas inlet within the expanding channel and positioned to provide a gas flow through the expanding channel in a circular direction, such as a vortex, a helix, a spiral or derivatives thereof. The expanding channel may be formed directly within the chamber lid or formed within a funnel liner attached thereon. The chamber may contain a retaining ring, an upper process liner, a lower process liner or a slip valve liner. Liners usually have a polished surface finish and contain a thermally insulating material such as fused quartz or ceramic. In an alternative embodiment, a deposition system contains a catalytic water vapor generator connected to an ALD chamber.
摘要翻译：本发明的实施例提供了在诸如原子层沉积（ALD）的气相沉积工艺期间在衬底上沉积材料的设备和方法。在一个实施例中，腔室包含具有接收表面的衬底支撑件和包含形成在绝热材料内的扩张通道的腔室盖。腔室还包括至少一个管道，其连接到膨胀通道内的气体入口并且定位成提供在圆形方向（例如涡流，螺旋，螺旋或其衍生物）上的气流通过膨胀通道。膨胀通道可以直接形成在室盖内，或者形成在其内附着的漏斗衬套中。腔室可以包含保持环，上加工衬套，下工艺衬垫或滑阀衬套。衬里通常具有抛光表面光洁度并且包含绝热材料，例如熔融石英或陶瓷。在替代实施例中，沉积系统包含连接到ALD室的催化水蒸汽发生器。

5. 发明授权

US07547952B2 Method for hafnium nitride deposition 失效
标题翻译：氮化铪沉积方法
公开(公告)号：US07547952B2
公开(公告)日：2009-06-16
申请号：US11420928
申请日：2006-05-30
申请人： Craig Metzner , Shreyas Kher , Yeong Kwan Kim , M. Noel Rocklein , Steven M. George
发明人： Craig Metzner , Shreyas Kher , Yeong Kwan Kim , M. Noel Rocklein , Steven M. George
IPC分类号： H01L29/72 , H01L21/3205 , H01L21/4763 , H01L21/31 , H01L21/469 , H01L21/10 , H01L21/26
CPC分类号： H01L21/0228 , C23C16/308 , C23C16/34 , C23C16/40 , C23C16/45531 , H01L21/02148 , H01L21/02205 , H01L21/02208 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/318 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.
摘要翻译：本发明通常是形成高k电介质层的方法，包括通过原子层沉积将铪化合物沉积到衬底上，包括将铪前体输送到衬底的表面，使铪前体反应并形成铪将含氮的前体输送到含铪层，形成至少一个铪氮键并将铪化合物沉积到表面。

6. 发明申请

US20080044569A1 METHODS FOR ATOMIC LAYER DEPOSITION OF HAFNIUM-CONTAINING HIGH-K DIELECTRIC MATERIALS 失效
标题翻译：含铪高K介电材料的原子层沉积方法
公开(公告)号：US20080044569A1
公开(公告)日：2008-02-21
申请号：US11925681
申请日：2007-10-26
申请人： Nyi Myo , Kenric Cho , Shreyas Kher , Pravin Narwankar , Steve Poppe , Craig Metzner , Paul Deaten
发明人： Nyi Myo , Kenric Cho , Shreyas Kher , Pravin Narwankar , Steve Poppe , Craig Metzner , Paul Deaten
IPC分类号： C23C16/00
CPC分类号： C23C16/4488 , C23C16/0272 , C23C16/40 , C23C16/401 , C23C16/405 , C23C16/4412 , C23C16/45529 , C23C16/45531 , C23C16/45544 , C23C16/45582 , C23C16/56 , Y02T50/67 , Y10T137/0357 , Y10T137/0396 , Y10T137/2087
摘要： Embodiments of the invention provide methods for depositing materials on substrates during vapor deposition processes, such as atomic layer deposition (ALD). In one embodiment, a chamber contains a substrate support with a receiving surface and a chamber lid containing an expanding channel formed within a thermally insulating material. The chamber further includes at least one conduit coupled to a gas inlet within the expanding channel and positioned to provide a gas flow through the expanding channel in a circular direction, such as a vortex, a helix, a spiral, or derivatives thereof. The expanding channel may be formed directly within the chamber lid or formed within a funnel liner attached thereon. The chamber may contain a retaining ring, an upper process liner, a lower process liner or a slip valve liner. Liners usually have a polished surface finish and contain a thermally insulating material such as fused quartz or ceramic. In an alternative embodiment, a deposition system contains a catalytic water vapor generator connected to an ALD chamber.
摘要翻译：本发明的实施例提供了在诸如原子层沉积（ALD）的气相沉积工艺期间在衬底上沉积材料的方法。在一个实施例中，腔室包含具有接收表面的衬底支撑件和包含形成在绝热材料内的扩张通道的腔室盖。腔室还包括至少一个管道，其连接到膨胀通道内的气体入口并且定位成提供在圆形方向（例如涡流，螺旋，螺旋或其衍生物）上的气体流过膨胀通道。膨胀通道可以直接形成在室盖内，或者形成在其内附着的漏斗衬套中。腔室可以包含保持环，上加工衬套，下工艺衬垫或滑阀衬套。衬里通常具有抛光表面光洁度并且包含绝热材料，例如熔融石英或陶瓷。在替代实施例中，沉积系统包含连接到ALD室的催化水蒸汽发生器。

7. 发明授权

US07910446B2 Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices 有权
标题翻译：用于形成用于非易失性存储器件的多晶硅电介质的集成方案
公开(公告)号：US07910446B2
公开(公告)日：2011-03-22
申请号：US12163542
申请日：2008-06-27
申请人： Yi Ma , Shreyas Kher , Khaled Ahmed
发明人： Yi Ma , Shreyas Kher , Khaled Ahmed
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324
摘要： Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.
摘要翻译：提供了用于形成电子器件的电子器件和方法，其允许减小器件尺寸，同时还保持或减少用于非易失性存储器件的漏电流。在一个实施例中，提供了一种制造非易失性存储器件的方法。该方法包括在衬底上沉积浮栅多晶硅层，在浮栅多晶硅层上形成氧化硅层，在氧化硅层上沉积第一氮氧化硅层，在第一氮氧化硅上沉积高k电介质材料层在所述高k电介质材料上沉积第二氮氧化硅，以及在所述第二氮氧化硅层上形成控制栅极多晶硅层。在一个实施例中，高k电介质材料层包括铪硅氮氧化物。

8. 发明申请

US20060264067A1 SURFACE PRE-TREATMENT FOR ENHANCEMENT OF NUCLEATION OF HIGH DIELECTRIC CONSTANT MATERIALS 审中-公开
标题翻译：用于增强高介电常数材料的表面预处理
公开(公告)号：US20060264067A1
公开(公告)日：2006-11-23
申请号：US11456062
申请日：2006-07-06
申请人： Shreyas Kher , Shixue Han , Craig Metzner
发明人： Shreyas Kher , Shixue Han , Craig Metzner
IPC分类号： H01L21/31
CPC分类号： H01L21/02312 , C23C16/0218 , C23C16/0227 , C23C16/405 , C23C16/509 , C23C16/56 , H01L21/02148 , H01L21/02181 , H01L21/02304 , H01L21/02307 , H01L21/31604 , H01L21/31612 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31683
摘要： Embodiments of the present invention relate to a surface preparation treatment for the formation of thin films of high k dielectric materials over substrates. One embodiment of a method of forming a high k dielectric layer over a substrate includes pre-cleaning a surface of a substrate to remove native oxides, pre-treating the surface of the substrate with a hydroxylating agent, and forming a high k dielectric layer over the surface of the substrate. One embodiment of a method of forming a hafnium containing layer over a substrate includes introducing an acid solution to a surface of a substrate, introducing a hydrogen containing gas and an oxygen containing gas to the surface of the substrate, and forming a hafnium containing layer over the substrate.
摘要翻译：本发明的实施例涉及用于在基板上形成高k电介质材料的薄膜的表面处理。在衬底上形成高k电介质层的方法的一个实施例包括预清洁衬底的表面以去除天然氧化物，用羟基化剂预处理衬底的表面，以及形成高k电介质层衬底的表面。在衬底上形成含铪层的方法的一个实施方案包括将酸溶液引入衬底的表面，将含氢气体和含氧气体引入衬底的表面，并且形成含铪层底物。

9. 发明申请

US20060062917A1 Vapor deposition of hafnium silicate materials with tris(dimethylamino)silane 审中-公开
标题翻译：硅酸铪材料与三（二甲基氨基）硅烷的蒸汽沉积
公开(公告)号：US20060062917A1
公开(公告)日：2006-03-23
申请号：US11223896
申请日：2005-09-09
申请人： Shankar Muthukrishnan , Tejal Goyani , Rahul Sharangpani , Shreyas Kher , Pravin Narwankar , Khaled Ahmed , Yi Ma
发明人： Shankar Muthukrishnan , Tejal Goyani , Rahul Sharangpani , Shreyas Kher , Pravin Narwankar , Khaled Ahmed , Yi Ma
IPC分类号： C23C16/00
CPC分类号： C23C16/308 , C23C16/401 , C23C16/56
摘要： In one embodiment, a method for forming a morphologically stable dielectric material is provided which includes exposing a substrate to a hafnium precursor, a silicon precursor and an oxidizing gas to form hafnium silicate material during a chemical vapor deposition (CVD) process and subsequently and optionally exposing the substrate to a post deposition anneal, a nitridation process and a thermal annealing process. In some examples, the hafnium and silicon precursors used during a metal-organic CVD (MOCVD) process are alkylamino compounds, such as tetrakis(diethylamino)hafnium (TDEAH) and tris(dimethylamino)silane (Tris-DMAS). In another embodiment, other metal precursors may be used to form a variety of metal silicates containing tantalum, titanium, aluminum, zirconium, lanthanum or combinations thereof.
摘要翻译：在一个实施方案中，提供了一种用于形成形态稳定的电介质材料的方法，其包括在化学气相沉积（CVD）工艺期间将衬底暴露于铪前体，硅前体和氧化气体以形成硅酸铪材料，随后和任选地将衬底暴露于后沉积退火，氮化工艺和热退火工艺。在一些实例中，在金属 - 有机CVD（MOCVD）方法中使用的铪和硅前体是烷基氨基化合物，例如四（二乙基氨基）铪（TDEAH）和三（二甲氨基）硅烷（Tris-DMAS）。在另一个实施方案中，其它金属前体可用于形成含有钽，钛，铝，锆，镧或其组合的各种金属硅酸盐。

10. 发明申请

US20050260357A1 Stabilization of high-k dielectric materials 有权
标题翻译：高k电介质材料的稳定化
公开(公告)号：US20050260357A1
公开(公告)日：2005-11-24
申请号：US10851514
申请日：2004-05-21
申请人： Christopher Olsen , Pravin Narwankar , Shreyas Kher , Randhir Thakur , Shankar Muthukrishnan , Philip Kraus
发明人： Christopher Olsen , Pravin Narwankar , Shreyas Kher , Randhir Thakur , Shankar Muthukrishnan , Philip Kraus
IPC分类号： C23C16/40 , C23C16/455 , C23C16/56 , H01L21/28 , H01L21/314 , H01L21/316 , B05D7/00
CPC分类号： H01L21/3141 , C23C16/401 , C23C16/405 , C23C16/45529 , C23C16/56 , H01L21/28202 , H01L21/3143 , H01L21/31637 , H01L21/31645 , H01L29/517
摘要： In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.
摘要翻译：在一个实施例中，提供了一种在衬底上形成电介质堆叠的方法，其包括在衬底表面上沉积介电材料的第一层，将第一层暴露于氮化工艺，将第二层介电材料沉积在第一层，将第二层暴露于氮化工艺，并将衬底暴露于退火工艺。在另一个实施例中，提供了一种用于在衬底上形成介电材料的方法，其包括在衬底表面上沉积基本上不含硅的金属氧化物层，将金属氧化物层暴露于氮化工艺，以及将衬底暴露于退火工艺。

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