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1. 发明授权

US06858542B2 Semiconductor fabrication method for making small features 有权
标题翻译：制造小功能的半导体制造方法
公开(公告)号：US06858542B2
公开(公告)日：2005-02-22
申请号：US10346263
申请日：2003-01-17
申请人： Terry G. Sparks , Ajay Singhal , Kirk J. Strozewski
发明人： Terry G. Sparks , Ajay Singhal , Kirk J. Strozewski
IPC分类号： G01N20060101 , G03F7/00 , G03F7/36 , H01L21/027 , H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： H01L21/3085 , H01L21/3083 , H01L21/31144 , Y10S438/947 , Y10S438/976 , Y10S438/978
摘要： A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.
摘要翻译：一种半导体制造方法，包括在半导体衬底（102）上形成包括成像层（112）和下层（110）的膜（109）。成像层（112）被图案化以产生具有印刷尺寸（124）的印刷特征（116）。然后，下层（110）被处理以在下层（110）中产生倾斜的侧壁空隙（120），其中空隙（120）具有接近底层基底的成品尺寸（126），小于印刷尺寸。处理底层（110）可以包括将晶片暴露于高密度低压N2等离子体。

2. 发明授权

US07487492B1 Method for increasing manufacturability of a circuit layout 有权
标题翻译：提高电路布局可制造性的方法
公开(公告)号：US07487492B1
公开(公告)日：2009-02-03
申请号：US11437312
申请日：2006-05-19
申请人： Ajay Singhal , Todd Lukanc
发明人： Ajay Singhal , Todd Lukanc
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： According to one exemplary embodiment, a method for increasing manufacturability of a circuit layer includes determining a threshold value for at least one image property from a repetitive section of the circuit layout. According to this embodiment, the method further includes performing a simulated lithographic process using the circuit layout to determine a number of simulated values of the at least one image property for a non-repetitive section of the circuit layout. The method further includes comparing each of the simulated values with the threshold value to determine printability of the non-repetitive section of the circuit layout prior to lithographically printing the circuit layout on a wafer. The method further includes modifying the non-repetitive section of the circuit layout if the threshold value is greater than at least one of the simulated values. By modifying the non-repetitive section of the circuit layout, manufacturability of the circuit layout can be increased.
摘要翻译：根据一个示例性实施例，用于提高电路层的可制造性的方法包括从电路布局的重复部分确定至少一个图像特性的阈值。根据本实施例，该方法还包括使用电路布局来执行模拟光刻处理，以确定电路布局的非重复部分的至少一个图像特性的模拟值的数量。该方法还包括将每个模拟值与阈值进行比较，以在光刻印刷晶片上的电路布局之前确定电路布局的非重复部分的可印刷性。该方法还包括如果阈值大于至少一个模拟值，则修改电路布局的非重复部分。通过修改电路布局的非重复部分，可以提高电路布局的可制造性。

3. 发明授权

US5985680A Method and apparatus for transforming a substrate coordinate system into a wafer analysis tool coordinate system 失效
标题翻译：将基板坐标系转换成晶片分析工具坐标系的方法和装置
公开(公告)号：US5985680A
公开(公告)日：1999-11-16
申请号：US907590
申请日：1997-08-08
申请人： Ajay Singhal , Yuri Uritsky , Patrick D. Kinney
发明人： Ajay Singhal , Yuri Uritsky , Patrick D. Kinney
IPC分类号： G01N21/94 , G03F7/20 , G03F9/00 , H01L21/00
CPC分类号： H01L21/67288 , G01N21/94 , G03F7/7065 , G03F9/70
摘要： A method and apparatus for accurately transforming coordinates within a first coordinate system (e.g., a two-dimensional coordinate system associated with a substrate (or portion thereof)) into coordinates in a second coordinate system (e.g., a three-dimensional coordinate system of substrate (or portion thereof) tilted within a wafer analysis tool.
摘要翻译：一种用于将第一坐标系（例如，与衬底（或其部分）相关联的二维坐标系）中的坐标精确地变换为第二坐标系（例如，衬底的三维坐标系）的坐标的方法和装置（或其部分）在晶片分析工具内倾斜。

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