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1. 发明申请

WO2020161456A1 ELECTRONIC AUTHENTICATION SYSTEM, DEVICE AND PROCESS 审中-公开
公开(公告)号：WO2020161456A1
公开(公告)日：2020-08-13
申请号：PCT/GB2019/052097
申请日：2019-07-26
申请人： ARM LIMITED , APICAL LIMITED
发明人： CROXFORD, Daren , MENDEZ, Roberto Lopez , EYOLE, Mbou , HORSNELL, Matthew James
IPC分类号： G06F21/32 , G06F3/01
摘要： Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques for authenticating an identity of a subject. In particular, some embodiments are directed to techniques for authentication of an identity of a subject as being an identity of a particular unique individual based, at least in part, on involuntary responses by the subject to sensory stimuli.

2. 发明申请

WO2021175481A1 DECOUPLED ACCESS-EXECUTE PROCESSING AND PREFETCHING CONTROL 审中-公开
公开(公告)号：WO2021175481A1
公开(公告)日：2021-09-10
申请号：PCT/EP2020/087542
申请日：2020-12-21
申请人： ARM LIMITED
发明人： EYOLE, Mbou , VAN TOL, Michiel Willem , KAXIRAS, Stefanos
IPC分类号： G06F9/345 , G06F9/38
摘要： Apparatuses and methods are provided, relating to the control of data processing in devices which comprise both decoupled access-execute processing circuitry and prefetch circuitry. Control of the access portion of the decoupled access-execute processing circuitry may be dependent on a performance metric of the prefetch circuitry. Alternatively or in addition, control of the prefetch circuitry may be dependent on a performance metric of the access portion.

3. 发明申请

WO2019069042A1 HANDLING ERRORS IN BUFFERS 审中-公开
公开(公告)号：WO2019069042A1
公开(公告)日：2019-04-11
申请号：PCT/GB2018/052450
申请日：2018-08-30
申请人： ARM LIMITED
发明人： VENU, Balaji , BOETTCHER, Matthias Lothar , EYOLE, Mbou
IPC分类号： G06F11/16 , G06F11/18 , G06F11/22 , G06F11/267
摘要： A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.

4. 发明申请

WO2019025754A1 COUNTING ELEMENTS IN DATA ITEMS IN A DATA PROCESSING APPARATUS 审中-公开
公开(公告)号：WO2019025754A1
公开(公告)日：2019-02-07
申请号：PCT/GB2018/052001
申请日：2018-07-13
申请人： ARM LIMITED
发明人： VICENTE, Alejandro Martinez , BEU, Jesse Garrett , EYOLE, Mbou , HAYES, Timothy
IPC分类号： G06F9/30
摘要： An apparatus and method of operating the apparatus are provided for performing a count operation. Instruction decoder circuitry is responsive to a count instruction specifying an input data item to generate control signals to control the data processing circuitry to perform a count operation. The count operation determines a count value indicative of a number of input elements of a subset of elements in the specified input data item which have a value which matches a reference value in a reference element in a reference data item. A plurality of count operations may be performed to determine a count data item corresponding to the input data item. A register scatter storage instruction, a gather index generation instruction, and respective apparatuses responsive to them, as well as simulator implementations are also provided.

5. 发明申请

WO2018109428A1 REPLICATE ELEMENTS INSTRUCTION 审中-公开
公开(公告)号：WO2018109428A1
公开(公告)日：2018-06-21
申请号：PCT/GB2017/053395
申请日：2017-11-10
申请人： ARM LIMITED
发明人： EAPEN, Jacob , MAGKLIS, Grigorios , EYOLE, Mbou
IPC分类号： G06F9/30
摘要： A replicate elements instruction defining a plurality of variable length segments in a result vector controls processing circuitry (80) to generate a result vector in which, in each respective segment, a repeating value is repeated throughout that segment of the result vector, the repeating value comprising a data value or element index of a selected data element of a source vector. This instructions is useful for accelerating processing of data structures smaller than the vector length.

6. 发明申请

WO2021079085A1 ONLINE INSTRUCTION TAGGING 审中-公开
公开(公告)号：WO2021079085A1
公开(公告)日：2021-04-29
申请号：PCT/GB2020/052481
申请日：2020-10-08
申请人： ARM LIMITED
发明人： EYOLE, Mbou , VAN TOL, Michiel Willem
IPC分类号： G06F9/30 , G06F9/38
摘要： Apparatuses and methods of data processing are disclosed for tagging instructions on-line. Instruction tag storage stores information indicative of a tag applied to certain instruction identifiers. A data processing operation performed by the data processing circuitry in response to an executed instruction is dependent on whether there is a corresponding instruction identifier for the executed instruction in the instruction tag storage which has the instruction tag. Register writer storage is maintained, and an entry is created for each register writing instruction encountered which causes a result value to be written to a destination register, where the entry comprises an indication of the destination register and the register writing instruction. An instruction tagging queue buffers instruction identifiers and an instruction identifier is added to the queue for a predetermined type of instruction when it is encountered. Instruction tagging circuitry tags the instructions in the instruction tagging queue and determines one or more producer instructions which each produce at least one data value which is a source operand of a subject instruction and adds the one or more producer instructions to the instruction tagging queue. Data dependency graphs are thus elaborated and online tagging of such data dependency graphs is thus supported.

7. 发明申请

WO2021078630A1 DECOUPLED ACCESS-EXECUTE PROCESSING 审中-公开
公开(公告)号：WO2021078630A1
公开(公告)日：2021-04-29
申请号：PCT/EP2020/079097
申请日：2020-10-15
申请人： ARM LIMITED
发明人： EYOLE, Mbou , KAXIRAS, Stefanos
IPC分类号： G06F9/30 , G06F9/38
摘要： Apparatuses and methods of data processing are disclosed. An apparatus comprises first instruction execution circuitry, second instruction execution circuitry, and a decoupled access buffer. Instructions of an ordered sequence of instructions are issued to one of the first and second instruction execution circuitry for execution in dependence on whether the instruction has a first type label or a second type label. An instruction with the first type label is an access-related instruction which determines at least one characteristic of a load operation to retrieve a data value from a memory address. Instruction execution by the first instruction execution circuitry of instructions having the first type label is prioritised over instruction execution by the second instruction execution circuitry of instructions having the second type label. Data values retrieved from memory as a result of execution of the first type instructions are stored in the decoupled access buffer. Once a data value needed for execution of a pending second type instruction is in the decoupled access buffer, the second instruction execution circuitry retrieves the data value from the decoupled access buffer and executes the pending instruction.

8. 发明申请

WO2021078515A1 APPARATUS AND METHOD FOR HANDLING MEMORY LOAD REQUESTS 审中-公开
公开(公告)号：WO2021078515A1
公开(公告)日：2021-04-29
申请号：PCT/EP2020/078095
申请日：2020-10-07
申请人： ARM LIMITED
发明人： EYOLE, Mbou , KAXIRAS, Stefanos
IPC分类号： G06F9/38 , G06F9/30
摘要： Apparatuses and methods of data processing are disclosed. When load requests are generated to support data processing operations, the load requests are buffered in pending load buffer circuitry prior to being carried out. Coalescing circuitry determines for a first load request whether a set of one or more subsequent load requests buffered in the pending load buffer circuitry satisfies an address proximity condition. The address proximity condition is satisfied when all data items identified by the set of one or more subsequent load requests are comprised within a series of data items which will be retrieved from the memory system in response to the first load request. When the address proximity condition is satisfied, forwarding of the set of one or more subsequent load requests is suppressed. On receipt of the series of data items retrieved by load handling circuitry decoalescing circuitry returns the data item identified by the load request and, when the address proximity condition is satisfied, one or more further data items for the one or more subsequent load requests.

9. 发明申请

WO2019115142A1 VECTOR ADD-WITH-CARRY INSTRUCTION 审中-公开
公开(公告)号：WO2019115142A1
公开(公告)日：2019-06-20
申请号：PCT/EP2018/081444
申请日：2018-11-15
申请人： ARM LIMITED
发明人： EYOLE, Mbou , STEPHENS, Nigel John , BURGESS, Neil , MAGKLIS, Grigorios
IPC分类号： G06F9/30
摘要： Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.

10. 发明申请

WO2019025752A1 MATCHING CONSECUTIVE VALUES IN A DATA PROCESSING APPARATUS 审中-公开
公开(公告)号：WO2019025752A1
公开(公告)日：2019-02-07
申请号：PCT/GB2018/051897
申请日：2018-07-05
申请人： ARM LIMITED
发明人： VICENTE, Alejandro Martinez , BEU, Jesse Garrett , EYOLE, Mbou , HAYES, Timothy
IPC分类号： G06F7/02 , G06F9/30
摘要： An apparatus and a method of operating the apparatus are provided for performing a comparison operation to match a given sequence of values within an input vector. Instruction decoder circuitry is responsive to a string match instruction specifying a segment of an input vector to generate control signals to control the data processing circuitry to perform a comparison operation. The comparison operation determines a comparison value indicative of whether each input element of a required set of consecutive input elements of the segment has a value which matches a respective value in consecutive reference elements of the reference data item. A plurality of comparison operations may be performed to determine a match vector corresponding to the segment of the input vector to indicate the start position of the substring in the input vector. A string match instruction, as well as simulator virtual machine implementations, are also provided.

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