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1. 发明申请

WO2022090690A1 HIGH-PRECISION ANCHORED-IMPLICIT PROCESSING 审中-公开
公开(公告)号：WO2022090690A1
公开(公告)日：2022-05-05
申请号：PCT/GB2021/052729
申请日：2021-10-21
申请人： ARM LIMITED
发明人： BURGESS, Neil , HINDS, Christopher Neal , LUTZ, David Raymond , FERREIRA, Pedro Olsen
IPC分类号： G06F7/485 , G06F7/544
摘要： An apparatus includes a processing circuit and a storage device. The processing circuit is configured to perform one or more processing operations in response to one or more instructions to generate an anchored-data element. The storage device is configured to store the anchored-data element. A format of the anchored-data element includes an identification item, an overlap item, and a data item. The data item is configured to hold a data value of the anchored-data element. The identification item indicates an anchor value for the data value or one or more special values.

2. 发明申请

WO2016071664A1 DATA PROCESSING APPARATUS AND METHOD USING PROGRAMMABLE SIGNIFICANCE DATA 审中-公开
标题翻译：数据处理设备和使用可编程意义数据的方法
公开(公告)号：WO2016071664A1
公开(公告)日：2016-05-12
申请号：PCT/GB2015/052701
申请日：2015-09-18
申请人： ARM LIMITED
发明人： LUTZ, David Raymond , HINDS, Christopher Neal , BURGESS, Neil
IPC分类号： G06F9/30 , G06F7/48 , G06F7/38
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： An apparatus may have processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement.
摘要翻译：装置可以具有处理电路，以执行用于基于至少一个操作数产生结果值的一个或多个算术运算。对于至少一个算术运算，处理电路响应于指示结果值的目标有效性的可编程有效数据，以产生具有目标有效性的结果值。例如，这允许程序员设置算术运算的显着边界，使得处理电路不需要计算具有超出指定边界的重要性的位值，从而能够提高性能。

3. 发明申请

WO2013083957A1 APPARATUS AND METHOD FOR ROUNDING A FLOATING-POINT VALUE TO AN INTEGRAL FLOATING-POINT VALUE 审中-公开
标题翻译：将浮点值转换为整体浮点值的装置和方法
公开(公告)号：WO2013083957A1
公开(公告)日：2013-06-13
申请号：PCT/GB2012/052938
申请日：2012-11-29
申请人： ARM LIMITED
发明人： LUTZ, David Raymond , BURGESS, Neil , ROMERO, Sabrina Marie
IPC分类号： G06F7/499
CPC分类号： G06F7/49947 , G06F7/49957
摘要： Processing circuitry is provided to perform an operation FRINT for rounding a floating-point value to an integral floating-point value. Control circuitry controls the processing circuitry to perform the FRINT operation in response to an FRINT instruction. The processing circuitry includes shifting circuitry for generating a rounding value by shifting a base value, adding circuitry for adding the rounding value to the significand of the floating-point value to generate a sum value, mask generating circuitry for generating a mask for clearing fractional-valued bits of the sum value,and masking circuitry for applying the mask to the sum value to generate the integral floating-point value.
摘要翻译：提供处理电路以执行用于将浮点值舍入为整数浮点值的操作FRINT。控制电路控制处理电路，以响应于FRINT指令执行FRINT操作。处理电路包括用于通过移位基值产生舍入值的移位电路，用于将舍入值加到浮点值的有效位数的相加电路以生成和值，用于产生用于清除分数位数的掩码的掩码生成电路，和值的值比特;以及掩蔽电路，用于将掩模应用于和值以生成积分浮点值。

4. 发明申请

WO2017081434A1 REDUNDANT REPRESENTATION OF NUMERIC VALUE USING OVERLAP BITS 审中-公开
标题翻译：使用重叠位冗余表示数值
公开(公告)号：WO2017081434A1
公开(公告)日：2017-05-18
申请号：PCT/GB2016/051499
申请日：2016-05-25
申请人： ARM LIMITED
发明人： BURGESS, Neil , LUTZ, David Raymond , HINDS, Christopher Neal
IPC分类号： G06F7/50
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/50 , G06F7/5095 , G06F2207/4924
摘要： A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits of each N-bit, and within a group of at least two adjacent N-bit portions, two or more overlap bits of a lower N-bit portion of the group have a same significance as two or more least significant bits of at least one upper N-bit portion of the group. A plurality of operation circuit units can perform a plurality of independent N-bit operation in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation. This enables fast associative processing of relatively long M-bit values in the time taken for performing an N-bit operation.
摘要翻译：提供冗余表示，其中M位值表示使用多个N位部分的P位数值，其中M> P> N。锚值标识每个N比特的比特的重要性，并且在至少两个相邻N比特部分的组内，该组的较低N比特部分的两个或更多个重叠比特具有与两个或更多个比特相同的重要性，或者该组的至少一个高N位部分的更多最低有效位。多个操作电路单元可以并行地执行多个独立的N位操作，每个N位操作包括计算具有冗余表示的至少两个M位操作数值的对应N位部分的函数，以生成具有冗余表示的M位结果值的相应N位部分。这使得能够在执行N位操作所需的时间内快速关联处理相对较长的M位值。

5. 发明申请

WO2016071668A1 VECTOR OPERANDS WITH ELEMENTS REPRESENTING DIFFERENT BIT PORTIONS OF AN INTEGER 审中-公开
标题翻译：具有代表整数的不同位元素的元素的向量运算
公开(公告)号：WO2016071668A1
公开(公告)日：2016-05-12
申请号：PCT/GB2015/052733
申请日：2015-09-22
申请人： ARM LIMITED
发明人： LUTZ, David, Raymond , BURGESS, Neil , HINDS, Christopher, Neal
IPC分类号： G06F9/30 , G06F7/48 , G06F7/38
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system supports vector operands on a plurality of elements each representing different bit portions of a single integer number. Processing circuitry performs a processing operation specified by a program instruction in dependence upon a number of elements comprising the bit portions as specified by metadata for the vector.
摘要翻译：数据处理系统支持多个元素上的向量操作数，每个元素表示单个整数的不同比特部分。处理电路根据由向量的元数据指定的包括位部分的元素的数量执行由程序指令指定的处理操作。

6. 发明申请

WO2016071662A1 APPARATUS AND METHOD FOR PERFORMING A FLOATING POINT CONVERSION OPERATION 审中-公开
标题翻译：用于执行浮点转换操作的装置和方法
公开(公告)号：WO2016071662A1
公开(公告)日：2016-05-12
申请号：PCT/GB2015/052699
申请日：2015-09-18
申请人： ARM LIMITED
发明人： LUTZ, David Raymond , BURGESS, Neil , HINDS, Christopher Neal
IPC分类号： G06F9/30 , G06F7/48
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： An apparatus comprises processing circuitry to perform a conversion operation to convert a floating-point value to a vector comprising a plurality of data elements representing respective bit significance portions of a two's complement format fixed point value corresponding to the sign-magnitude format floating-point value.
摘要翻译：一种装置包括处理电路，以执行转换操作以将浮点值转换成包括多个数据元素的向量，所述多个数据元素表示对应于符号幅度格式浮点值的二进制补码格式固定点值的相应位重要部分。

7. 发明公开

EP3912272A1 ANCHORED DATA ELEMENT CONVERSION 审中-实审
公开(公告)号：EP3912272A1
公开(公告)日：2021-11-24
申请号：EP20704345.6
申请日：2020-01-30
申请人： ARM Limited
发明人： LUTZ, David Raymond , BURGESS, Neil , HINDS, Christopher Neal , STEPHENS, Nigel John
IPC分类号： H03M7/24 , G06F9/30

8. 发明申请

WO2020161457A1 OVERFLOW OR UNDERFLOW HANDLING FOR ANCHORED-DATA VALUE 审中-公开
公开(公告)号：WO2020161457A1
公开(公告)日：2020-08-13
申请号：PCT/GB2019/053363
申请日：2019-11-28
申请人： ARM LIMITED
发明人： LUTZ, David, Raymond , BURGESS, Neil , HINDS, Christopher, Neal
IPC分类号： G06F9/30 , G06F9/38
摘要： Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.

9. 发明申请

WO2019115142A1 VECTOR ADD-WITH-CARRY INSTRUCTION 审中-公开
公开(公告)号：WO2019115142A1
公开(公告)日：2019-06-20
申请号：PCT/EP2018/081444
申请日：2018-11-15
申请人： ARM LIMITED
发明人： EYOLE, Mbou , STEPHENS, Nigel John , BURGESS, Neil , MAGKLIS, Grigorios
IPC分类号： G06F9/30
摘要： Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.

10. 发明申请

WO2018115807A1 VECTOR GENERATING INSTRUCTION 审中-公开
公开(公告)号：WO2018115807A1
公开(公告)日：2018-06-28
申请号：PCT/GB2017/053355
申请日：2017-11-08
申请人： ARM LIMITED
发明人： BOTMAN, François Christopher Jacques , GROCUTT, Thomas Christopher , BURGESS, Neil
IPC分类号： G06F9/30 , G06F9/345 , G06F9/355
摘要： An apparatus and method are provided for performing vector processing operations. In particular the apparatus has processing circuitry to perform the vector processing operations and an instruction decoder to decode vector instructions to control the processing circuitry to perform the vector processing operations specified by the vector instructions. The instruction decoder is responsive to a vector generating instruction identifying a scalar start value and wrapping control information, to control the processing circuitry to generate a vector comprising a plurality of elements. In particular, the processing circuitry is arranged to generate the vector such that the first element in the plurality is dependent on the scalar start value, and the values of the plurality of elements follow a regularly progressing sequence that is constrained to wrap as required to ensure that each value is within bounds determined from the wrapping control information. The vector generating instruction can be useful in a variety of situations, a particular use case being to implement a circular addressing mode within memory, where the vector generating instruction can be coupled with an associated vector memory access instruction. Such an approach can remove the need to provide additional logic within the memory access path to support such circular addressing.

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