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1. 发明申请

WO2019115142A1 VECTOR ADD-WITH-CARRY INSTRUCTION 审中-公开
公开(公告)号：WO2019115142A1
公开(公告)日：2019-06-20
申请号：PCT/EP2018/081444
申请日：2018-11-15
申请人： ARM LIMITED
发明人： EYOLE, Mbou , STEPHENS, Nigel John , BURGESS, Neil , MAGKLIS, Grigorios
IPC分类号： G06F9/30
摘要： Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.

2. 发明申请

WO2019063203A1 TRANSACTION NESTING DEPTH TESTING INSTRUCTION 审中-公开
公开(公告)号：WO2019063203A1
公开(公告)日：2019-04-04
申请号：PCT/EP2018/072560
申请日：2018-08-21
申请人： ARM LIMITED
发明人： MAGKLIS, Grigorios , HORSNELL, Matthew James , DIESTELHORST, Stephan
IPC分类号： G06F9/38 , G06F9/30
摘要： In a system providing transactional memory support, a transaction nesting depth testing instruction is provided for triggering processing circuitry (4) to set at least one status value to one of a plurality of states depending on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth is 1 and at least one further state selected when the transaction nesting depth is greater than or less than 1. The ISA supported enables the setting of the at least one status value and a conditional branch conditional on the at least one status value being in the first state to be performed in response to a single transaction nesting depth testing instruction and a single conditional branch instruction.

3. 发明申请

WO2018001643A1 PERMISSION CONTROL FOR CONTINGENT MEMORY ACCESS PROGRAM INSTRUCTION 审中-公开
标题翻译：或然存储器访问程序指令的许可控制
公开(公告)号：WO2018001643A1
公开(公告)日：2018-01-04
申请号：PCT/EP2017/062043
申请日：2017-05-18
申请人： ARM LIMITED
发明人： STEPHENS, Nigel John , MAGKLIS, Grigorios
IPC分类号： G06F21/79 , G06F12/14
摘要： A data processing apparatus and method serve to manage access permission checking in respect of contingent memory access operations (the access permission failure of which does not alter program flow) in dependence of a contingent-access permission checking disable flag. If the contingent access disable flag has a first value, then this disables memory permission circuitry e.g. a walk state machine 22, from performing a check as to whether or not the memory access circuitry is permitted to perform a requested memory access. Non-contingent memory accesses are able to utilise the memory permission circuitry irrespective of the value of the contingent-access permission checking disable flag.
摘要翻译：数据处理装置和方法用于根据临时存取权限检查禁止来管理关于临时存储器存取操作（其存取权限故障不改变程序流）的存取权限检查旗。如果临时访问禁止标志具有第一值，则这将禁止存储器许可电路，例如，步行状态机22执行关于是否允许存储器访问电路执行所请求的存储器访问的检查。无条件存储器访问能够利用存储器许可电路，而不管条件访问权限检查禁止标志的值如何。

4. 发明申请

WO2020012151A1 TRANSACTIONAL COMPARE-AND-DISCARD INSTRUCTION 审中-公开
公开(公告)号：WO2020012151A1
公开(公告)日：2020-01-16
申请号：PCT/GB2019/051275
申请日：2019-05-09
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , MAGKLIS, Grigorios , DIESTELHORST, Stephan
IPC分类号： G06F9/30 , G06F9/38
摘要： An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry. In response to a transactional compare-and-discard instruction executed within a given transaction, specifying a target address and a compare value, the processing circuitry loads a target data value from a memory location corresponding to the target address; sets at least one condition status indication depending on a result of comparing the target data value and the compare value; and discards the target data value without adding the target address to a working set of addresses tracked for the given transaction. This is useful for enabling thread level speculation to be implemented on a transactional memory architecture.

5. 发明申请

WO2020002869A1 HANDLING LOAD-EXCLUSIVE INSTRUCTIONS IN APPARATUS HAVING SUPPORT FOR TRANSACTIONAL MEMORY 审中-公开
公开(公告)号：WO2020002869A1
公开(公告)日：2020-01-02
申请号：PCT/GB2019/051276
申请日：2019-05-09
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , MAGKLIS, Grigorios , GRISENTHWAITE, Richard Roy , CHONG, Nathan Yong Seng
IPC分类号： G06F9/30 , G06F9/38 , G06F9/52
摘要： An apparatus is described with support for transactional memory and load/store- exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.

6. 发明申请

WO2017021269A1 VECTOR PROCESSING USING LOOPS OF DYNAMIC VECTOR LENGTH 审中-公开
标题翻译：使用动态矢量长度的矢量处理
公开(公告)号：WO2017021269A1
公开(公告)日：2017-02-09
申请号：PCT/EP2016/068013
申请日：2016-07-28
申请人： ARM LIMITED
发明人： STEPHENS, Nigel John , MAGKLIS, Grigorios , PREMILLIEU, Nathanael , MARTINEZ VICENTE, Alejandro , EYOLE, Mbou
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30076 , G06F9/3836
摘要： Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.
摘要翻译：数据处理装置包括：处理电路，根据与位置相关联的各个谓词标志的状态，在向量处理操作中选择性地对数据向量中包含多个数据项的数据向量的一个或多个数据项进行应用; 所述处理电路包括：解码程序指令的指令解码器电路; 以及指令处理电路，用于执行由指令解码器电路解码的指令; 其中指令解码器电路响应于WHILE指令和CHANGE指令，以依赖于多个谓词标志来控制指令处理。

7. 发明申请

WO2017021055A1 VECTOR LENGTH QUERYING INSTRUCTION 审中-公开
标题翻译：向量长度查询指令
公开(公告)号：WO2017021055A1
公开(公告)日：2017-02-09
申请号：PCT/EP2016/064500
申请日：2016-06-23
申请人： ARM LIMITED
发明人： STEPHENS, Nigel John , MAGKLIS, Grigorios , MARTINEZ-VICENTE, Alejandro , PREMILLIEU, Nathanael
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30003 , G06F9/3001 , G06F9/30036 , G06F9/3004
摘要： A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.
摘要翻译：支持向量处理操作的数据处理系统2使用缩放向量长度查询指令。缩放向量长度查询指令返回结果，该结果取决于由指令指定的可变向量元素大小的向量中的元素数量，并乘以指令指定的缩放值。缩放向量长度查询指令可以是计数指令，递增指令或递减指令的形式。指令可以包括对表示为指令指定的寄存器元素大小提供的向量元素的数量的部分结果值应用诸如模（M）或2的幂的约束的模式约束。

8. 发明申请

WO2019011653A1 TESTING BIT VALUES INSIDE VECTOR ELEMENTS 审中-公开
公开(公告)号：WO2019011653A1
公开(公告)日：2019-01-17
申请号：PCT/EP2018/067234
申请日：2018-06-27
申请人： ARM LIMITED
发明人： MAGKLIS, Grigorios , STEPHENS, Nigel John
IPC分类号： G06F9/30
摘要： An apparatus and method of operating an apparatus are provided. The apparatus is responsive to a bit-testing instruction which specifies a source vector register and an index to perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits. The bit-testing procedure comprises, for each processed element of the plural elements, setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index. This bit-testing instruction thus enables increased performance of program code which is required to perform multiple bit tests and can be suitably formulated into a vectorised form.

9. 发明申请

WO2019001896A1 ADDRESS TRANSLATION DATA INVALIDATION 审中-公开
公开(公告)号：WO2019001896A1
公开(公告)日：2019-01-03
申请号：PCT/EP2018/064497
申请日：2018-06-01
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , MAGKLIS, Grigorios , GRISENTHWAITE, Richard Roy
IPC分类号： G06F12/1027
摘要： A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

10. 发明申请

WO2018109428A1 REPLICATE ELEMENTS INSTRUCTION 审中-公开
公开(公告)号：WO2018109428A1
公开(公告)日：2018-06-21
申请号：PCT/GB2017/053395
申请日：2017-11-10
申请人： ARM LIMITED
发明人： EAPEN, Jacob , MAGKLIS, Grigorios , EYOLE, Mbou
IPC分类号： G06F9/30
摘要： A replicate elements instruction defining a plurality of variable length segments in a result vector controls processing circuitry (80) to generate a result vector in which, in each respective segment, a repeating value is repeated throughout that segment of the result vector, the repeating value comprising a data value or element index of a selected data element of a source vector. This instructions is useful for accelerating processing of data structures smaller than the vector length.

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