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1. 发明申请

WO2020161456A1 ELECTRONIC AUTHENTICATION SYSTEM, DEVICE AND PROCESS 审中-公开
公开(公告)号：WO2020161456A1
公开(公告)日：2020-08-13
申请号：PCT/GB2019/052097
申请日：2019-07-26
申请人： ARM LIMITED , APICAL LIMITED
发明人： CROXFORD, Daren , MENDEZ, Roberto Lopez , EYOLE, Mbou , HORSNELL, Matthew James
IPC分类号： G06F21/32 , G06F3/01
摘要： Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques for authenticating an identity of a subject. In particular, some embodiments are directed to techniques for authentication of an identity of a subject as being an identity of a particular unique individual based, at least in part, on involuntary responses by the subject to sensory stimuli.

2. 发明申请

WO2019001896A1 ADDRESS TRANSLATION DATA INVALIDATION 审中-公开
公开(公告)号：WO2019001896A1
公开(公告)日：2019-01-03
申请号：PCT/EP2018/064497
申请日：2018-06-01
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , MAGKLIS, Grigorios , GRISENTHWAITE, Richard Roy
IPC分类号： G06F12/1027
摘要： A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

3. 发明申请

WO2016097681A1 MONITORING UTILIZATION OF TRANSACTIONAL PROCESSING RESOURCE 审中-公开
标题翻译：监测交易处理资源的利用
公开(公告)号：WO2016097681A1
公开(公告)日：2016-06-23
申请号：PCT/GB2015/053570
申请日：2015-11-24
申请人： ARM LIMITED
发明人： DIESTELHORST, Stephan , HORSNELL, Matthew James
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/467 , G06F9/3842 , G06F11/362
摘要： An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed speculatively following a transaction start event and for which the speculative results are committed in response to a transaction end event. Monitoring circuitry (30) captures monitoring data indicating a degree of utilization of the transactional processing resource (10, 18) when processing the transaction.
摘要翻译：设备（2）可以具有用于执行数据访问操作以从至少一个存储设备（10,12,14）访问数据的处理元件（4）。处理元件可以具有至少一个支持事务处理的事务处理资源（10,18），其中数据访问在事务开始事件之后被推测地执行，并且响应于事务结束事件提供推测结果。当处理交易时，监视电路（30）捕获指示事务处理资源（10,18）的利用程度的监控数据。

4. 发明申请

WO2022034293A1 MONITORING MEMORY LOCATIONS TO IDENTIFY WHETHER DATA STORED AT THE MEMORY LOCATIONS HAS BEEN MODIFIED 审中-公开
公开(公告)号：WO2022034293A1
公开(公告)日：2022-02-17
申请号：PCT/GB2021/052030
申请日：2021-08-05
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James
IPC分类号： G06F12/0811 , G06F12/0831 , G06F12/084 , G06F9/38 , G06F9/52
摘要： An apparatus comprises address storage circuitry to store indications of a first set of memory locations of a shared memory; a capacity indicator to indicate whether a capacity of the address storage circuitry has been reached, and monitoring circuitry to monitor the first set of memory locations and a second set of memory locations of the shared memory, identified in further storage circuitry to identify whether data stored at either set of memory locations has been modified. The monitoring circuitry is responsive to determining that the data has been modified to generate an indication that the data has been modified, and processing circuitry receives the indication and executes a monitor-address instruction specifying an address of a new memory location in the shared memory to update the address storage circuitry or the further storage circuitry to indicate the new address, depending on the capacity indicator.

5. 发明申请

WO2019135063A1 SPECULATION BARRIER INSTRUCTION 审中-公开
公开(公告)号：WO2019135063A1
公开(公告)日：2019-07-11
申请号：PCT/GB2018/053636
申请日：2018-12-14
申请人： ARM LIMITED
发明人： GRISENTHWAITE, Richard Roy , GABRIELLI, Giacomo , HORSNELL, Matthew James
IPC分类号： G06F9/30 , G06F12/08 , G06F12/14 , G06F9/38
CPC分类号： G06F9/30196 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30058 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F12/0875 , G06F12/1491 , G06F21/71 , G06F2212/1052
摘要： An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry to perform the data processing. The instruction decoding circuitry is responsive to a speculation barrier instruction to control the processing circuitry to prevent a subsequent operation, appearing in program order after the speculation barrier instruction, that has an address dependency on an earlier instruction preceding the speculation barrier instruction in the program order, from speculatively influencing allocations of entries in a cache. This provides protection against speculative cache-timing side-channel attacks.

6. 发明申请

WO2016102919A1 DEBUGGING DATA PROCESSING TRANSACTIONS 审中-公开
标题翻译：调查数据处理交易
公开(公告)号：WO2016102919A1
公开(公告)日：2016-06-30
申请号：PCT/GB2015/053559
申请日：2015-11-23
申请人： ARM LIMITED
发明人： DIESTELHORST, Stephan , WILLIAMS, Michael John , GRISENTHWAITE, Richard Roy , HORSNELL, Matthew James
IPC分类号： G06F11/36
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/3834 , G06F9/3842 , G06F9/455 , G06F9/46 , G06F9/467 , G06F11/362 , G06F11/3636 , G06F12/08 , G06F12/126
摘要： A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.
摘要翻译：提供支持执行包括执行以产生推测更新的一个或多个程序指令的事务的数据处理系统。如果事务完成而没有冲突，则推测更新在正常操作中提交。可以检测到事务的执行开始，并且执行被转移以由软件仿真执行，而不是由处理硬件直接执行。软件仿真可以存储表示仿真期间生成的推测性更新的一个或多个版本的数据。软件仿真还可以检测与被仿真的事务的冲突。为了便于修改与被调查的事务相互作用的系统的其他部分的行为，可以响应于被仿真的事务的检测到的存储器访问请求而返回非标准响应信号。可以使用非标准响应信号来启动请求源以跟随不同于其将遵循的处理路径的后续路径。还提供支持以检测导致部分完成的事务的停止（冻结）的触发条件，并且将与部分完成的事务相关联的推测更新保存到系统的体系结构状态。

7. 发明申请

WO2013072657A1 SIMD INSTRUCTIONS FOR SUPPORTING GENERATION OF HASH VALUES IN CRYPTOGRAPHIC ALGORITHMS 审中-公开
标题翻译：用于支持CRYPTOGRAPHIC算法中HASH值生成的SIMD指令
公开(公告)号：WO2013072657A1
公开(公告)日：2013-05-23
申请号：PCT/GB2012/052315
申请日：2012-09-20
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , GRISENTHWAITE, Richard Roy , KERSHAW, Daniel , BILES, Stuart David
IPC分类号： G06F9/30 , G06F9/38 , H04L9/08
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/12 , H04L2209/125
摘要： A data processing system (2) includes a single instruction multiple data register file (12) and single instruction multiple processing circuitry (14). The single instruction multiple data processing circuitry (14) supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file (12). The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
摘要翻译：数据处理系统（2）包括单指令多数据寄存器文件（12）和单指令多处理电路（14）。单指令多数据处理电路（14）支持执行用于执行散列算法部分的密码处理指令。操作数存储在单指令多数据寄存器文件（12）中。加密支持指令不遵循正常的基于通道的处理，并且生成输出操作数，其中输出操作数的不同部分取决于输入操作数中的多个不同元素。

8. 发明申请

WO2019197811A1 EXCEPTION HANDLING IN TRANSACTIONS 审中-公开
公开(公告)号：WO2019197811A1
公开(公告)日：2019-10-17
申请号：PCT/GB2019/051020
申请日：2019-04-08
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , MAGKLIS, Grigorios , DIESTELHORST, Stephan
IPC分类号： G06F9/46 , G06F11/14
摘要： An apparatus and a method of operating a data processing apparatus, and simulators thereof, are disclosed. Data processing circuitry performs data processing operations in response to instructions, where some sets of instructions may be defined as a transaction which are to be performed atomically with respect to other operations performed by the data processing circuitry. When a synchronous exception occurs during a transaction the transaction is aborted and an exception counter is incremented. When the counter reaches a threshold value a transaction failure signal is generated, allowing, if appropriate a response to this number of exceptions causing transaction aborts to be carried out.

9. 发明申请

WO2019073192A1 CHECKING LOCK VARIABLES FOR TRANSACTIONS IN A SYSTEM WITH TRANSACTIONAL MEMORY SUPPORT 审中-公开
公开(公告)号：WO2019073192A1
公开(公告)日：2019-04-18
申请号：PCT/GB2018/052452
申请日：2018-08-30
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , DIESTELHORST, Stephan
IPC分类号： G06F9/46 , G06F9/52 , G06F9/30 , G06F9/38
摘要： In an apparatus (2) with transactional memory support, a predetermined type of transaction start instruction or a subsequent instruction following the predetermined type of transaction start instruction triggers capture of a lock identifier which identifies a lock variable for controlling exclusive access to at least one resource. In response to a predetermined type of transaction end instruction which follows the predetermined type of transaction start instruction, the lock variable is checked and commitment of results of speculatively executed instructions of the transaction is prevented or deferred when the lock variable indicates that another thread holds the exclusive access to the target resource. This approach can improve performance when executing transactions in a transactional memory based system.

10. 发明申请

WO2018055326A1 HANDLING OF INTER-ELEMENT ADDRESS HAZARDS FOR VECTOR INSTRUCTIONS 审中-公开
标题翻译：处理向量元素地址危险向量说明
公开(公告)号：WO2018055326A1
公开(公告)日：2018-03-29
申请号：PCT/GB2017/052387
申请日：2017-08-14
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , EYOLE, Mbou
IPC分类号： G06F9/30
摘要： An apparatus has processing circuitry (4) supporting vector load and store instructions. In response to a transaction start event, the processing circuitry executes one or more subsequent instructions speculatively. In response to a transaction end event, the processing circuitry (4) commits speculative results of those instructions. Hazard detection circuitry (50) detects whether an inter-element address hazard occurs between an address for data element J for an earlier vector load instruction and an address for data element K for a later vector store instruction, where K and J are not equal. In response to detecting the inter-element address hazard, the hazard detection circuitry (50) triggers the processing circuitry (4) to abort further processing of the instructions following the transaction start event and to prevent the speculative results being committed. This approach can provide faster performance for vectorised code.
摘要翻译：处理电路（4）支持矢量加载和存储指令。响应于事务开始事件，处理电路推测性地执行一个或多个后续指令。响应于事务结束事件，处理电路（4）提交这些指令的推测结果。危险检测电路（50）检测在较早的向量加载指令的数据元素J的地址与稍后的向量存储指令的数据元素K的地址之间是否发生元件间地址危险，其中K和J不相等。响应于检测到元件间地址危险，危险检测电路（50）触发处理电路（4）中止事务开始事件之后的指令的进一步处理，并防止提交推测结果。这种方法可以为矢量化代码提供更快的性能。

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