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1. 发明申请

WO2022101600A1 FILTERING BASED ON A RANGE SPECIFIER 审中-公开
公开(公告)号：WO2022101600A1
公开(公告)日：2022-05-19
申请号：PCT/GB2021/052397
申请日：2021-09-16
申请人： ARM LIMITED
发明人： BOTMAN, Francois Christopher Jacques , GROCUTT, Thomas Christopher , SMITH, Bradley John
IPC分类号： G06F7/02 , G06F7/483
摘要： Data processing apparatuses, methods and computer programs are disclosed. A range definition register is arranged to store a range specifier and filtering operations are performed with respect to a specified transaction by reference to the range definition register. The range definition register stores the range specifier in a format comprising a significand and an exponent, wherein a range of data identifiers is at least partially defined by the range specifier. When the specified transaction is with respect to a data identifier within the range of data identifiers, the filtering operations performed are dependent on attribute data associated with the range of data identifiers.

2. 发明申请

WO2021156589A1 APPARATUS AND METHOD FOR CAPABILITY-BASED PROCESSING 审中-公开
公开(公告)号：WO2021156589A1
公开(公告)日：2021-08-12
申请号：PCT/GB2020/053093
申请日：2020-12-02
申请人： ARM LIMITED
发明人： SMITH, Bradley John , GROCUTT, Thomas Christopher , BOTMAN, François Christopher Jacques
IPC分类号： G06F21/52 , G06F9/30 , G06F12/14
摘要： Apparatus comprises a processor to execute program instructions stored at respective memory addresses, processing of the program instructions being constrained by a prevailing capability defining at least access permissions to a set of one or more memory addresses; the processor comprising: control flow change handling circuitry to perform a control flow change operation, the control flow change operation defining a control flow change target address indicating the address of a program instruction for execution after the control flow change operation; and capability generating circuitry to determine, in dependence on the control flow change target address, an address at which capability access permissions data is stored; the capability generating circuitry being configured to retrieve the capability access permissions data and to generate a capability for use as a next prevailing capability in dependence upon at least the capability access permissions data.

3. 发明申请

WO2021156588A1 SAVING AND RESTORING REGISTERS AND METADATA 审中-公开
公开(公告)号：WO2021156588A1
公开(公告)日：2021-08-12
申请号：PCT/GB2020/053011
申请日：2020-11-26
申请人： ARM LIMITED
发明人： SMITH, Bradley John , GROCUTT, Thomas Christopher
IPC分类号： G06F9/30 , G06F9/34 , G06F9/46 , G06F21/60
摘要： There is provided a data processing apparatus comprising a plurality of registers, each of the registers having data bits to store data and metadata bits to store metadata. Each of the registers is adapted to operate in a metadata mode in which the metadata bits and the data bits are valid, and a data mode in which the data bits are valid and the metadata bits are invalid. Mode bit storage circuitry indicates whether each of the registers is in the data mode or the metadata mode. Execution circuitry is responsive to a memory operation that is a store operation on one or more given registers to (i) determine from the mode bit storage circuitry whether a register in the one or more given registers is in the data mode or the metadata mode, (ii) store the data bits of the register and the metadata bits of the register to a data structure in memory when the register is in the metadata mode, and (iii) store the data bits of the register without the metadata bits of the register to the data structure in the memory when the register is in the data mode.

4. 发明申请

WO2021116653A1 INTERMODAL CALLING BRANCH INSTRUCTION 审中-公开
公开(公告)号：WO2021116653A1
公开(公告)日：2021-06-17
申请号：PCT/GB2020/052797
申请日：2020-11-05
申请人： ARM LIMITED
发明人： GROCUTT, Thomas Christopher
IPC分类号： G06F9/30 , G06F9/38 , G06F21/00
摘要： Processing circuitry (4) has a handler mode and a thread mode. In response to an exception condition, a switch to handler mode is made. In response to an intermodal calling branch instruction specifying a branch target address when the processing circuitry (4) is in the handler mode, an instruction decoder (10) controls the processing circuitry to save a function return address to a function return address storage location; switch a current mode of the processing circuitry (4) to the thread mode; and branch to an instruction identified by the branch target address. This can be useful for deprivileging of exceptions.

5. 发明申请

WO2019106355A1 ENCODING OF INPUT TO STORAGE CIRCUITRY 审中-公开
公开(公告)号：WO2019106355A1
公开(公告)日：2019-06-06
申请号：PCT/GB2018/053433
申请日：2018-11-28
申请人： ARM LIMITED
发明人： REID, Alastair David , MULLIGAN, Dominic , MERIAC, Milosch , BOETTCHER, Matthias Lothar , CHONG, Nathan Young Seng , CAULFIELD, Ian Michael , GREENHALGH, Peter Richard , PIRY, Frederic Claude Marie , TONNERRE, Albin Pierrick , GROCUTT, Thomas Christopher , ISHII, Yasuo
IPC分类号： G06F9/38 , G06F21/00
CPC分类号： G06F21/556 , G06F9/3806 , G06F9/3842 , G06F9/3851 , G06F12/10 , G06F21/53 , G06F21/78 , G06F2212/65 , G06F2221/034 , H04L9/0643
摘要： A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

6. 发明申请

WO2015052477A1 CUMULATIVE ERROR DETECTION IN DATA TRANSMISSION 审中-公开
标题翻译：数据传输中的累积误差检测
公开(公告)号：WO2015052477A1
公开(公告)日：2015-04-16
申请号：PCT/GB2014/052476
申请日：2014-08-13
申请人： ARM LIMITED
发明人： GROCUTT, Thomas Christopher , AMOS, Dall George Mathew
IPC分类号： H03M13/09
CPC分类号： G06F11/1004 , H03M13/09 , H03M13/091 , H04L1/0041 , H04L1/0061
摘要： Circuitry for providing error check values for indicating errors in data portions within a data stream. The circuitry comprises error detecting code generation circuitry configured to apply an error detecting code algorithm to the data stream and to thereby generate and periodically update a multi-bit check value as the data stream is processed, each update of the multi-bit check value being indicative of the error detecting code generation circuitry receiving a further item of the data stream. An output for periodically outputting a fragment of the multi-bit check value from the error detecting code generation circuitry during the processing of the data stream, the fragments output each corresponding to a data portion of the data stream. Wherein each of the fragment of the multi-bit check value provides a value indicative of an error occurring either in the corresponding portion of the data stream or in an earlier portion of the data stream.
摘要翻译：用于提供用于指示数据流内的数据部分中的错误的错误检查值的电路。所述电路包括错误检测代码生成电路，所述错误检测代码生成电路经配置以将错误检测代码算法应用于所述数据流，并且由此在处理所述数据流时生成并周期性地更新多位检查值，所述多位检查值的每次更新为指示错误检测码产生电路接收数据流的另一个项目。一种输出，用于在数据流的处理期间周期性地从错误检测码产生电路输出多比特校验值的片段，每个与数据流的数据部分相对应的片段输出。其中，多位检查值的每个片段提供指示在数据流的相应部分或数据流的较早部分中出现的错误的值。

7. 发明申请

WO2014053802A1 DATA PROCESSING APPARATUS AND METHOD USING SECURE DOMAIN AND LESS SECURE DOMAIN 审中-公开
标题翻译：数据处理设备和使用安全域和较少安全域的方法
公开(公告)号：WO2014053802A1
公开(公告)日：2014-04-10
申请号：PCT/GB2013/052105
申请日：2013-08-07
申请人： ARM LIMITED
发明人： GROCUTT, Thomas Christopher , GRISENTHWAITE, Richard, Roy
IPC分类号： G06F21/52
CPC分类号： G06F21/629 , G06F21/50 , G06F21/52 , G06F21/54 , G06F21/554 , G06F21/74 , G06F2221/2105
摘要： A data processing apparatus (2) has processing circuitry (4) which has a secure domain and a less secure domain of operation. When operating in the secure domain the processing circuitry (4) has access to data that is not accessible in the less secure domain. In response to a control flow altering instruction, processing switches to a program instruction at a target address. Domain selection is performed to determine a selected domain in which the processing circuitry (4) is to operate for the instruction at the target address. Domain checking can be performed to check which domains are allowed to be the selected domain determining the domain selection. A domain check error is triggered if the selected domain in the domain selection is not an allowed selected domain.
摘要翻译：数据处理装置（2）具有处理电路（4），其具有安全域和较不安全的操作区域。当在安全域中操作时，处理电路（4）可访问在较不安全的域中不可访问的数据。响应于控制流改变指令，处理切换到目标地址处的程序指令。执行域选择以确定处理电路（4）将在目标地址处的指令操作的选定域。可以执行域检查以检查哪些域被允许作为确定域选择的所选域。如果域选择中的选定域不是允许的选定域，则会触发域检查错误。

8. 发明申请

WO2022234243A1 TECHNIQUE FOR CONSTRAINING ACCESS TO MEMORY USING CAPABILITIES 审中-公开
公开(公告)号：WO2022234243A1
公开(公告)日：2022-11-10
申请号：PCT/GB2022/050430
申请日：2022-02-17
申请人： ARM LIMITED
发明人： BOTMAN, François Christopher Jacques , GROCUTT, Thomas Christopher , SMITH, Bradley John
IPC分类号： G06F12/14 , G06F12/1036 , G06F12/02
摘要： There is provided an apparatus, method and computer program for constraining memory accesses. The apparatus comprises processing circuitry to perform operations during which access requests to memory are generated. The processing circuitry is arranged to generate memory addresses for the access requests using capabilities that identify constraining information. The apparatus further comprises capability checking circuitry to perform a capability check operation to determine whether a given access request whose memory address is generated using a given capability is permitted based on given constraining information identified by the given capability. The capability check operation includes performing a range check based on range constraining information provided by the given constraining information, and when a determined condition is met, to perform the range check in dependence on both the range constraining information and an item of state information of the apparatus which varies dynamically during performance of the operations of the processing circuitry.

9. 发明申请

WO2021152282A1 AN APPARATUS AND METHOD FOR CONTROLLING ACCESS TO A SET OF MEMORY MAPPED CONTROL REGISTERS 审中-公开
公开(公告)号：WO2021152282A1
公开(公告)日：2021-08-05
申请号：PCT/GB2020/053326
申请日：2020-12-21
申请人： ARM LIMITED
发明人： GROCUTT, Thomas Christopher
IPC分类号： G06F9/30 , G06F12/14
摘要： A technique is described for controlling access to a set of memory mapped control registers. An apparatus has processing circuitry for executing program code in order to perform data processing operations, and a set of memory mapped control registers for storing control information used to control operation of the processing circuitry when executing the program code. Further, a lockdown register is used to store a lockdown value. The processing circuitry is arranged to execute store instructions to perform write operations to a memory address space, the store instructions being of multiple types. However, when the lockdown value is set, the processing circuitry is arranged to prevent a write operation being performed to change the control information in the memory mapped control registers unless that write operation occurs due to execution of a store instruction from a first subset of the multiple types of store instructions. This significantly reduces the prospect of an attacker seeking to exploit a software vulnerability to change the control information in the memory mapped control registers.

10. 发明申请

WO2020079386A1 RANGE CHECKING INSTRUCTION 审中-公开
公开(公告)号：WO2020079386A1
公开(公告)日：2020-04-23
申请号：PCT/GB2019/052336
申请日：2019-08-20
申请人： ARM LIMITED
发明人： GROCUTT, Thomas Christopher
IPC分类号： G06F12/14
摘要： An apparatus (2) comprises: an instruction decoder (7) to decode instructions; processing circuitry (4) to perform data processing in response to the instructions decoded by the instruction decoder; and memory attribute checking circuitry (16) to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a plurality of memory attribute entries, each memory attribute entry specifying access permissions for a corresponding address region of variable size within an address space. In response to a range checking instruction specifying address identifying parameters for identifying a first address and a second address, the instruction decoder (7) controls the processing circuitry (4) to set, in at least one software-accessible storage location (12, 13); a status value indicative of whether the first address and the second address correspond to the same memory attribute entry.

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