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1. 发明申请

US20090217018A1 METHODS, APPARATUS AND ARTICLES OF MANUFACTURE FOR REGAINING MEMORY CONSISTENCY AFTER A TRAP VIA TRANSACTIONAL MEMORY 失效
标题翻译：方法，装置和制造商在通过交易记录进行跟踪之后记录一致性的制造
公开(公告)号：US20090217018A1
公开(公告)日：2009-08-27
申请号：US12037888
申请日：2008-02-26
申请人： ALEXANDER ABRASHKEVICH , Dmitri Abrashkevich , Robert J. Blainey , Thomas J. Heller, JR. , Matthew A. Huras , Sridhar Munireddy , Yogendra K. Srivastava , Mark F. Wilding
发明人： ALEXANDER ABRASHKEVICH , Dmitri Abrashkevich , Robert J. Blainey , Thomas J. Heller, JR. , Matthew A. Huras , Sridhar Munireddy , Yogendra K. Srivastava , Mark F. Wilding
IPC分类号： G06F9/44
CPC分类号： G06F9/467 , G06F11/1474
摘要： Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction.
摘要翻译：本发明的实施例提供一种通过事务存储器在陷阱之后恢复存储器一致性的方法。事务内存和事务性内存日志用于撤消从事务起始点到陷阱事件点对内存所做的更改。处理陷阱事件后，回滚更改，程序可以在事务开始时恢复执行。

2. 发明授权

US08032736B2 Methods, apparatus and articles of manufacture for regaining memory consistency after a trap via transactional memory 失效
标题翻译：用于通过事务记忆在陷阱之后恢复记忆一致性的方法，装置和制品
公开(公告)号：US08032736B2
公开(公告)日：2011-10-04
申请号：US12037888
申请日：2008-02-26
申请人： Alexander Abrashkevich , Dmitri Abrashkevich , Robert J. Blainey , Thomas J. Heller, Jr. , Matthew A. Huras , Sridhar Munireddy , Yogendra K. Srivastava , Mark F. Wilding
发明人： Alexander Abrashkevich , Dmitri Abrashkevich , Robert J. Blainey , Thomas J. Heller, Jr. , Matthew A. Huras , Sridhar Munireddy , Yogendra K. Srivastava , Mark F. Wilding
IPC分类号： G06F9/40 , G06F9/48
CPC分类号： G06F9/467 , G06F11/1474
摘要： Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction.
摘要翻译：本发明的实施例提供一种通过事务存储器在陷阱之后恢复存储器一致性的方法。事务内存和事务性内存日志用于撤消从事务起始点到陷阱事件点对内存所做的更改。处理陷阱事件后，回滚更改，程序可以在事务开始时恢复执行。

3. 发明授权

US09170844B2 Prioritization for conflict arbitration in transactional memory management 有权
标题翻译：事务性内存管理中冲突仲裁的优先级
公开(公告)号：US09170844B2
公开(公告)日：2015-10-27
申请号：US12348216
申请日：2009-01-02
申请人： Robert J. Blainey , C. Brian Hall , Thomas J. Heller, Jr. , Mark F. Wilding
发明人： Robert J. Blainey , C. Brian Hall , Thomas J. Heller, Jr. , Mark F. Wilding
IPC分类号： G06F9/50 , G06F9/52 , G06F9/46 , G06F13/16
CPC分类号： G06F9/5016 , G06F9/467 , G06F9/526 , G06F13/1605
摘要： Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system.
摘要翻译：本发明的实施例提供了一种用于在事务性存储器管理中的嵌入式冲突仲裁的并发事务的软件优先化的方法，系统和计算机程序产品。在本发明的一个实施例中，用于事务性存储器管理中的嵌入式冲突仲裁的并行事务的软件优先化的方法可以包括：根据相应的事务存储器管理配置用于事务性存储器管理的事务存储器系统中的相应不同的事务，设置具有不同优先级值的不同硬件寄存器通过外部软件对系统的优先级分配逻辑指定的优先级值。该方法还可以包括检测系统中的事务之间的冲突。最后，该方法可以包括基于在系统的外部软件支持中由优先级分配逻辑指定的优先级值在系统内应用冲突仲裁。

4. 发明申请

US20100174840A1 PRIORITIZATION FOR CONFLICT ARBITRATION IN TRANSACTIONAL MEMORY MANAGEMENT 有权
标题翻译：交易性内存管理中的冲突仲裁优先权
公开(公告)号：US20100174840A1
公开(公告)日：2010-07-08
申请号：US12348216
申请日：2009-01-02
申请人： Robert J. Blainey , C. Brian Hall , Thomas J. Heller, JR. , Mark F. Wilding
发明人： Robert J. Blainey , C. Brian Hall , Thomas J. Heller, JR. , Mark F. Wilding
IPC分类号： G06F13/374
CPC分类号： G06F9/5016 , G06F9/467 , G06F9/526 , G06F13/1605
摘要： Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system.
摘要翻译：本发明的实施例提供了一种用于在事务性存储器管理中的嵌入式冲突仲裁的并发事务的软件优先化的方法，系统和计算机程序产品。在本发明的一个实施例中，用于事务性存储器管理中的嵌入式冲突仲裁的并行事务的软件优先化的方法可以包括：根据相应的事务存储器管理配置用于事务性存储器管理的事务存储器系统中的相应不同的事务，设置具有不同优先权值的不同硬件寄存器通过外部软件对系统的优先级分配逻辑指定的优先级值。该方法还可以包括检测系统中的事务之间的冲突。最后，该方法可以包括基于在系统的外部软件支持中由优先级分配逻辑指定的优先级值在系统内应用冲突仲裁。

5. 发明授权

US08250315B2 Dynamic nest level determination for nested transactional memory rollback 有权
标题翻译：嵌套事务内存回滚的动态嵌套级别确定
公开(公告)号：US08250315B2
公开(公告)日：2012-08-21
申请号：US12348208
申请日：2009-01-02
申请人： Robert J. Blainey , C. Brian Hall
发明人： Robert J. Blainey , C. Brian Hall
IPC分类号： G06F12/00
CPC分类号： G06F9/466
摘要： Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.
摘要翻译：本发明的实施例解决了嵌套事务回滚方面的技术缺陷，并提供了一种用于嵌套事务回滚的动态嵌套级别确定的方法，系统和计算机程序产品。在本发明的实施例中，可以提供嵌套事务回滚方法。该方法可以包括检测在一组嵌套事务中访问的存储器块的违规，检索用于违规的暂时回滚级别，丢弃在该嵌套事务集合的每一级的存储块的投机状态，直到和/ 包括暂时的回滚级别，将一组嵌套事务中的初步回滚级别提高到较低级别，另外在嵌套事务集合中的额外级别中另外丢弃了内存块的推测状态，直到并包括精简回滚级别。

6. 发明授权

US09268598B2 Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories 有权
标题翻译：记录和分析交易失败源地址和对应于硬件事务存储器中止事务的地址的有效性指示符
公开(公告)号：US09268598B2
公开(公告)日：2016-02-23
申请号：US13615416
申请日：2012-09-13
申请人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
发明人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
IPC分类号： G06F9/46 , G06F11/14 , G06F11/36
CPC分类号： G06F9/467 , G06F11/1474 , G06F11/36 , G06F11/3648
摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.
摘要翻译：处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。事务存储器存储由处理器核心执行的多个事务的信息。处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

7. 发明授权

US08380941B2 Dynamic nest level determination for nested transactional memory rollback 失效
标题翻译：嵌套事务内存回滚的动态嵌套级别确定
公开(公告)号：US08380941B2
公开(公告)日：2013-02-19
申请号：US13411572
申请日：2012-03-04
申请人： Robert J. Blainey , C. Brian Hall
发明人： Robert J. Blainey , C. Brian Hall
IPC分类号： G06F12/00
CPC分类号： G06F9/466
摘要： Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.
摘要翻译：本发明的实施例解决了嵌套事务回滚方面的技术缺陷，并提供了一种用于嵌套事务回滚的动态嵌套级别确定的方法，系统和计算机程序产品。在本发明的实施例中，可以提供嵌套事务回滚方法。该方法可以包括检测在一组嵌套事务中访问的存储器块的违规，检索用于违规的暂时回滚级别，丢弃在该嵌套事务集合的每一级的存储器块的投机状态，直到和/ 包括暂时的回滚级别，将一组嵌套事务中的初步回滚级别提高到较低级别，另外在嵌套事务集合中的额外级别中另外丢弃了内存块的推测状态，直到并包括精简回滚级别。

8. 发明申请

US20120166747A1 DYNAMIC NEST LEVEL DETERMINATION FOR NESTED TRANSACTIONAL MEMORY ROLLBACK 失效
标题翻译：动态NEST级确定用于嵌入式交易式存储器ROLLBACK
公开(公告)号：US20120166747A1
公开(公告)日：2012-06-28
申请号：US13411572
申请日：2012-03-04
申请人： Robert J. Blainey , C. Brian Hall
发明人： Robert J. Blainey , C. Brian Hall
IPC分类号： G06F12/14
CPC分类号： G06F9/466
摘要： Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.
摘要翻译：本发明的实施例解决了嵌套事务回滚方面的技术缺陷，并提供了一种用于嵌套事务回滚的动态嵌套级别确定的方法，系统和计算机程序产品。在本发明的实施例中，可以提供嵌套事务回滚方法。该方法可以包括检测在一组嵌套事务中访问的存储器块的违规，检索用于违规的暂时回滚级别，丢弃在该嵌套事务集合的每一级的存储块的投机状态，直到和/ 包括暂时的回滚级别，将一组嵌套事务中的初步回滚级别提高到较低级别，另外在嵌套事务集合中的额外级别中另外丢弃了内存块的推测状态，直到并包括精简回滚级别。

9. 发明申请

US20100174874A1 DYNAMIC NEST LEVEL DETERMINATION FOR NESTED TRANSACTIONAL MEMORY ROLLBACK 有权
标题翻译：动态NEST级确定用于嵌入式交易式存储器ROLLBACK
公开(公告)号：US20100174874A1
公开(公告)日：2010-07-08
申请号：US12348208
申请日：2009-01-02
申请人： Robert J. Blainey , C. Brian Hall
发明人： Robert J. Blainey , C. Brian Hall
IPC分类号： G06F12/06
CPC分类号： G06F9/466
摘要： Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.
摘要翻译：本发明的实施例解决了嵌套事务回滚方面的技术缺陷，并提供了一种用于嵌套事务回滚的动态嵌套级别确定的方法，系统和计算机程序产品。在本发明的实施例中，可以提供嵌套事务回滚方法。该方法可以包括检测在一组嵌套事务中访问的存储器块的违规，检索用于违规的暂时回滚级别，丢弃在该嵌套事务集合的每一级的存储块的投机状态，直到和/ 包括暂时的回滚级别，将一组嵌套事务中的初步回滚级别提高到较低级别，另外在嵌套事务集合中的额外级别中另外丢弃了内存块的推测状态，直到并包括精简回滚级别。

10. 发明申请

US20140075441A1 METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES 有权
标题翻译：硬件交易记录中记录和分类交易失败源地址的方法和装置
公开(公告)号：US20140075441A1
公开(公告)日：2014-03-13
申请号：US13615416
申请日：2012-09-13
申请人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
发明人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F11/1474 , G06F11/36 , G06F11/3648
摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.
摘要翻译：处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。事务存储器存储由处理器核心执行的多个事务的信息。处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

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