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1. 发明申请

US20090300561A1 METHOD AND SYSTEM FOR POST-ROUTING LITHOGRAPHY-HOTSPOT CORRECTION OF A LAYOUT 有权
标题翻译：用于布线布局的方法和系统
公开(公告)号：US20090300561A1
公开(公告)日：2009-12-03
申请号：US12129617
申请日：2008-05-29
申请人： Yang-Shan Tong , Daniel Zhang , Linni Wei , Alex Miloslavsky , Wei-Chih Tseng , Zongwu Tang
发明人： Yang-Shan Tong , Daniel Zhang , Linni Wei , Alex Miloslavsky , Wei-Chih Tseng , Zongwu Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next, for each detected lithography hotspot, the system compares the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores a set of known hotspot configurations. If so, the system corrects the lithography hotspot using correction guidance information associated with the hotspot configuration stored in the hotspot database. Otherwise, the system corrects the lithography hotspot by performing a local rip-up and reroute on the local routing pattern, iteratively, until achieving convergence or given number of iterations.
摘要翻译：本发明的一个实施例提供一种验证集成电路（IC）芯片布局的系统。在操作过程中，系统在布局经过布线操作后接收IC芯片的布局。接下来，系统在布局上执行光刻柔性检查（LCC）操作以检测布局内的光刻热点，其中每个光刻热点与光刻热点周围的局部布线图案相关联。接下来，对于每个检测到的光刻热点，系统将相关联的本地路由模式与热点数据库进行比较，以确定本地路由模式是否匹配热点数据库中存储一组已知热点配置的条目。如果是，则系统使用与存储在热点数据库中的热点配置相关联的校正指导信息来校正光刻热点。否则，系统通过对本地路由模式执行局部的rip-up和重新路由来迭代地校正光刻热点，直到达到收敛或给定的迭代次数。

2. 发明授权

US08566754B2 Dual-purpose perturbation engine for automatically processing pattern-clip-based manufacturing hotspots 有权
标题翻译：用于自动处理基于图案片段的制造热点的双用途扰动引擎
公开(公告)号：US08566754B2
公开(公告)日：2013-10-22
申请号：US12275887
申请日：2008-11-21
申请人： Kent Y. Kwang , Daniel Zhang , Zongwu Tang , Subarnarekha Sinha
发明人： Kent Y. Kwang , Daniel Zhang , Zongwu Tang , Subarnarekha Sinha
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： One embodiment of the present invention provides a system that automatically processes manufacturing hotspot information. During operation, the system receives a pattern clip associated with a manufacturing hotspot in a layout, wherein the pattern clip comprises a set of polygons in proximity to the manufacturing hotspot's location. Next, the system determines if the pattern clip matches a known manufacturing hotspot configuration. If the pattern clip does not match a known manufacturing hotspot configuration, the system then performs a perturbation process on the pattern clip to determine a set of correction recommendations to eliminate the manufacturing hotspot. By performing the perturbation process, the system additionally determines ranges of perturbation to the set of polygons wherein the perturbed pattern clip does not eliminate the manufacturing hotspot. Subsequently, the system stores the set of correction recommendations and the ranges of perturbation into a manufacturing hotspot database.
摘要翻译：本发明的一个实施例提供一种自动处理制造热点信息的系统。在操作期间，系统接收与布局中的制造热点相关联的图案剪辑，其中图案剪辑包括靠近制造热点位置的一组多边形。接下来，系统确定模式剪辑是否匹配已知的制造热点配置。如果图案剪辑与已知的制造热点配置不匹配，则系统然后对图案剪辑执行扰动处理，以确定一组校正建议以消除制造热点。通过执行扰动过程，系统另外确定对该组多边形的扰动范围，其中扰动图案片不消除制造热点。随后，系统将修正建议的集合和扰动范围存储到制造热点数据库中。

3. 发明授权

US08458635B2 Convolution computation for many-core processor architectures 有权
标题翻译：多核处理器架构的卷积计算
公开(公告)号：US08458635B2
公开(公告)日：2013-06-04
申请号：US12631167
申请日：2009-12-04
申请人： Min Ni , Zongwu Tang , Qing Su
发明人： Min Ni , Zongwu Tang , Qing Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/68
摘要： A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.
摘要翻译：内核在多核处理器系统中的布局的卷积包括识别包括多个评估点的布局的称为动态带的扇区。指定布局扇区的布局数据被加载到由多个处理器核共享的共享存储器中。执行内核和扇区中评估点的卷积运算。卷积操作包括在给定指定扇区的布局数据的大小的情况下，将称为步幅的基础数据集的部分迭代地加载到共享存储器中可用的空间中。使用用于扇区的布局数据和基础数据集的当前加载的部分来同时执行多个线程。加载基础数据集的迭代通过整个数据集进行，直到卷积操作完成。

4. 发明申请

US20100014199A1 ELECTROSTATIC-DISCHARGE PROTECTION USING A MICRO-ELECTROMECHANICAL-SYSTEM SWITCH 有权
标题翻译：使用微机电系统开关进行静电放电保护
公开(公告)号：US20100014199A1
公开(公告)日：2010-01-21
申请号：US12176801
申请日：2008-07-21
申请人： Jamil Kawa , Subarnarekha Sinha , Min-Chun Tsai , ZongWu Tang , Qing Su
发明人： Jamil Kawa , Subarnarekha Sinha , Min-Chun Tsai , ZongWu Tang , Qing Su
IPC分类号： H02H9/04 , G06F17/50
CPC分类号： H01L27/0251 , H01H59/0009
摘要： Embodiments of an interface circuit are described. This interface circuit includes an input pad, a control node and a transistor, which has three terminals. A first terminal is electrically coupled to the input pad and a second terminal is electrically coupled to the control node. Moreover, the interface circuit includes a micro-electromechanical system (MEMS) switch, which is electrically coupled to the input pad and the control node, where the MEMS switch is in parallel with the transistor. In the absence of a voltage applied to a control terminal of the MEMS switch, the MEMS switch is closed, thereby electrically coupling the input pad and the control node. Furthermore, when the voltage is applied to the control terminal of the MEMS switch, the MEMS switch is open, thereby electrically decoupling the input pad and the control node.
摘要翻译：描述接口电路的实施例。该接口电路包括具有三个端子的输入焊盘，控制节点和晶体管。第一端子电耦合到输入焊盘，并且第二端子电耦合到控制节点。此外，接口电路包括微机电系统（MEMS）开关，其电耦合到输入焊盘和控制节点，其中MEMS开关与晶体管并联。在没有施加到MEMS开关的控制端子的电压的情况下，MEMS开关闭合，从而电耦合输入焊盘和控制节点。此外，当将电压施加到MEMS开关的控制端子时，MEMS开关断开，由此使输入焊盘和控制节点电耦合。

5. 发明授权

US07636904B2 Locating critical dimension(s) of a layout feature in an IC design by modeling simulated intensities 有权
标题翻译：通过建模模拟强度来确定IC设计中布局特征的关键维度
公开(公告)号：US07636904B2
公开(公告)日：2009-12-22
申请号：US11584356
申请日：2006-10-20
申请人： Hua Song , Lantiang Wang , ZongWu Tang
发明人： Hua Song , Lantiang Wang , ZongWu Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer is programmed to perform lithography simulation at a number of locations in a transverse direction relative to a length of a feature of an IC design, to obtain simulated intensities at the locations. The computer is further programmed to determine constants of a predetermined formula that models a trend of the simulated intensities as a function of distance (in the transverse direction), by curve-fitting. The computer is also programmed to compute a value (“CD predictor”) based on the just-determined constants, the formula and a known threshold intensity for a given position along the feature's length. The just-described process, of lithography-simulation, followed by curve-fitting, followed by CD predictor computation, is repeatedly performed to obtain a number of CD predictors at a corresponding number of positions along the feature's length. The CD predictors are used to identify a position of a critical dimension, for use in, for example, layout verification.
摘要翻译：计算机被编程为在相对于IC设计的特征的长度的横向方向上的多个位置处执行光刻模拟，以在位置处获得模拟的强度。计算机还被编程为通过曲线拟合来确定模拟强度的趋势作为距离（在横向方向上）的函数的预定公式的常数。计算机还被编程为基于刚刚确定的常数，公式和沿特征长度的给定位置的已知阈值强度来计算值（“CD预测器”）。重复执行刚才描述的光刻仿真过程，随后进行曲线拟合，随后进行CD预测器计算，以在沿着特征长度的相应位置的数量处获得多个CD预测器。 CD预测器用于识别临界尺寸的位置，用于例如布局验证。

6. 发明授权

US08877638B2 ESD/antenna diodes for through-silicon vias 有权
标题翻译：用于穿硅通孔的ESD /天线二极管
公开(公告)号：US08877638B2
公开(公告)日：2014-11-04
申请号：US13567922
申请日：2012-08-06
申请人： Jamil Kawa , Min Ni , James D. Sproch , Qing Su , Zongwu Tang
发明人： Jamil Kawa , Min Ni , James D. Sproch , Qing Su , Zongwu Tang
IPC分类号： H01L21/44 , H01L23/48 , H01L23/62 , H01L27/02 , H01L23/60 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/481 , H01L23/60 , H01L23/62 , H01L27/0207 , H01L27/0255 , H01L2225/06541 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.
摘要翻译：粗略地描述，天线二极管至少部分地形成在TSV周围的排阻区内，并且通过金属1层导体连接到TSV，同时TSV连接到栅极多晶硅或扩散层放置在排除区外的一个或多个晶体管的区域。

7. 发明申请

US20120295433A1 ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS 有权
标题翻译： ESD /天线二极管
公开(公告)号：US20120295433A1
公开(公告)日：2012-11-22
申请号：US13567922
申请日：2012-08-06
申请人： Qing Su , Min Ni , Zongwu Tang , Jamil Kawa , James D. Sproch
发明人： Qing Su , Min Ni , Zongwu Tang , Jamil Kawa , James D. Sproch
IPC分类号： H01L21/28
CPC分类号： G06F17/5068 , H01L23/481 , H01L23/60 , H01L23/62 , H01L27/0207 , H01L27/0255 , H01L2225/06541 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.
摘要翻译：粗略地描述，天线二极管至少部分地形成在TSV周围的排阻区内，并且通过金属1层导体连接到TSV，同时TSV连接到栅极多晶硅或扩散层放置在排除区外的一个或多个晶体管的区域。

8. 发明授权

US08264065B2 ESD/antenna diodes for through-silicon vias 有权
标题翻译：用于穿硅通孔的ESD /天线二极管
公开(公告)号：US08264065B2
公开(公告)日：2012-09-11
申请号：US12605102
申请日：2009-10-23
申请人： Qing Su , Min Ni , Zongwu Tang , Jamil Kawa , James D. Sproch
发明人： Qing Su , Min Ni , Zongwu Tang , Jamil Kawa , James D. Sproch
IPC分类号： H01L29/40 , H01L23/053 , H01L23/12 , H01L23/48 , H01L23/52 , H01L23/62
CPC分类号： G06F17/5068 , H01L23/481 , H01L23/60 , H01L23/62 , H01L27/0207 , H01L27/0255 , H01L2225/06541 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.
摘要翻译：粗略地描述，天线二极管至少部分地形成在TSV周围的排阻区内，并且通过金属1层导体连接到TSV，同时TSV连接到栅极多晶硅或扩散层放置在排除区外的一个或多个晶体管的区域。

9. 发明授权

US08037428B2 Method and system for post-routing lithography-hotspot correction of a layout 有权
标题翻译：布局布局光刻热点校正方法和系统
公开(公告)号：US08037428B2
公开(公告)日：2011-10-11
申请号：US12129617
申请日：2008-05-29
申请人： Yang-Shan Tong , Daniel Zhang , Linni Wei , Alex Miloslavsky , Wei-Chih Tseng , Zongwu Tang
发明人： Yang-Shan Tong , Daniel Zhang , Linni Wei , Alex Miloslavsky , Wei-Chih Tseng , Zongwu Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next, for each detected lithography hotspot, the system compares the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores a set of known hotspot configurations. If so, the system corrects the lithography hotspot using correction guidance information associated with the hotspot configuration stored in the hotspot database. Otherwise, the system corrects the lithography hotspot by performing a local rip-up and reroute on the local routing pattern, iteratively, until achieving convergence or given number of iterations.
摘要翻译：本发明的一个实施例提供一种验证集成电路（IC）芯片布局的系统。在操作过程中，系统在布局经过布线操作后接收IC芯片的布局。接下来，系统在布局上执行光刻柔性检查（LCC）操作以检测布局内的光刻热点，其中每个光刻热点与光刻热点周围的局部布线图案相关联。接下来，对于每个检测到的光刻热点，系统将相关联的本地路由模式与热点数据库进行比较，以确定本地路由模式是否匹配热点数据库中存储一组已知热点配置的条目。如果是，则系统使用与存储在热点数据库中的热点配置相关联的校正指导信息来校正光刻热点。否则，系统通过对本地路由模式执行局部的rip-up和重新路由来迭代地校正光刻热点，直到达到收敛或给定的迭代次数。

10. 发明授权

US07679872B2 Electrostatic-discharge protection using a micro-electromechanical-system switch 有权
标题翻译：使用微机电系统开关进行静电放电保护
公开(公告)号：US07679872B2
公开(公告)日：2010-03-16
申请号：US12176801
申请日：2008-07-21
申请人： Jamil Kawa , Subarnarekha Sinha , Min-Chun Tsai , ZongWu Tang , Qing Su
发明人： Jamil Kawa , Subarnarekha Sinha , Min-Chun Tsai , ZongWu Tang , Qing Su
IPC分类号： H02H9/04 , H02H9/00
CPC分类号： H01L27/0251 , H01H59/0009
摘要： Embodiments of an interface circuit are described. This interface circuit includes an input pad, a control node and a transistor, which has three terminals. A first terminal is electrically coupled to the input pad and a second terminal is electrically coupled to the control node. Moreover, the interface circuit includes a micro-electromechanical system (MEMS) switch, which is electrically coupled to the input pad and the control node, where the MEMS switch is in parallel with the transistor. In the absence of a voltage applied to a control terminal of the MEMS switch, the MEMS switch is closed, thereby electrically coupling the input pad and the control node. Furthermore, when the voltage is applied to the control terminal of the MEMS switch, the MEMS switch is open, thereby electrically decoupling the input pad and the control node.
摘要翻译：描述接口电路的实施例。该接口电路包括具有三个端子的输入焊盘，控制节点和晶体管。第一端子电耦合到输入焊盘，第二端子电耦合到控制节点。此外，接口电路包括微机电系统（MEMS）开关，其电耦合到输入焊盘和控制节点，其中MEMS开关与晶体管并联。在没有施加到MEMS开关的控制端子的电压的情况下，MEMS开关闭合，从而电耦合输入焊盘和控制节点。此外，当将电压施加到MEMS开关的控制端子时，MEMS开关断开，由此使输入焊盘和控制节点电耦合。

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