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1. 发明授权

US07994003B2 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07994003B2
公开(公告)日：2011-08-09
申请号：US12382646
申请日：2009-03-20
申请人： Byong-Ju Kim , Sun-Jung Kim , Zong-Liang Huo , Jun-Kyu Yang , Seon-Ho Jo , Han-Mei Choi , Young-Sun Kim
发明人： Byong-Ju Kim , Sun-Jung Kim , Zong-Liang Huo , Jun-Kyu Yang , Seon-Ho Jo , Han-Mei Choi , Young-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/02164 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/02337 , H01L21/02348 , H01L21/02356 , H01L21/28282 , H01L21/3141 , H01L21/31612 , H01L21/3162 , H01L21/84 , H01L29/42332 , H01L29/7881 , H01L29/792
摘要： A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on the tunnel insulating layer, forming a dielectric layer on the charge storage layer, the dielectric layer including a first aluminum oxide layer, a silicon oxide layer, and a second aluminum oxide layer sequentially stacked on the charge storage layer, and forming a gate electrode on the dielectric layer, the gate electrode directly contacting the second aluminum oxide layer of the dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道绝缘层，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成电介质层，电介质层包括第一氧化铝层，氧化硅层和第二氧化铝层，所述第二氧化铝层依次堆叠在所述电荷存储层上，并且在所述电介质层上形成栅电极，所述栅电极与所述电介质层的所述第二氧化铝层直接接触。

2. 发明申请

US20080246078A1 Charge trap flash memory device and memory card and system including the same 有权
标题翻译：充电陷阱闪存设备和存储卡及系统包括相同
公开(公告)号：US20080246078A1
公开(公告)日：2008-10-09
申请号：US12080315
申请日：2008-04-02
申请人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
发明人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7881
摘要： A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.
摘要翻译：提供了一种电荷阱闪存器件及其制造方法。该器件包括：隧道绝缘层，电荷陷阱层; 阻挡绝缘层; 以及依次形成在基板上的栅电极。电荷陷阱层包括：多个陷阱层，包括具有第一带隙能级的第一材料; 间隔开的纳米点，每个纳米点至少部分地被至少一个捕获层包围，其中该纳米点包括具有低于第一带隙能级的第二带隙能级的第二材料; 以及中间阻挡层，其包括形成在至少两个捕获层之间的具有高于第一带隙能级的第三带隙能级的第三材料。这种结构防止电荷陷阱层的电荷损失并且改善电荷存储容量。

3. 发明申请

US20060249770A1 Single Transistor Floating-Body DRAM Devices Having Vertical Channel Transistor Structures and Methods of Fabricating the Same 失效
标题翻译：具有垂直沟道晶体管结构的单晶体管浮动体DRAM器件及其制造方法
公开(公告)号：US20060249770A1
公开(公告)日：2006-11-09
申请号：US11380946
申请日：2006-05-01
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.
摘要翻译：单晶体体浮体DRAM器件具有垂直沟道晶体管结构。 DRAM器件包括衬底，以及设置在衬底上并彼此隔离的第一和第二浮体。源极区域和漏极区域设置在第一和第二浮体的每一个之下和之上。栅电极设置在第一和第二浮体之间。还提供了制造单晶体管浮体DRAM器件的方法。

4. 发明授权

US07982256B2 Semiconductor memory device having DRAM cell mode and non-volatile memory cell mode and operation method thereof 失效
标题翻译：具有DRAM单元模式和非易失性存储单元模式的半导体存储器件及其操作方法
公开(公告)号：US07982256B2
公开(公告)日：2011-07-19
申请号：US11798716
申请日：2007-05-16
申请人： Zong-Liang Huo , In-Seok Yeo
发明人： Zong-Liang Huo , In-Seok Yeo
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C7/1045 , G11C11/404 , H01L27/108 , H01L27/10802 , H01L29/7841 , H01L29/7881 , H01L29/792
摘要： A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.
摘要翻译：半导体存储器件可以具有DRAM单元模式和不具有电容器的非易失性存储单元模式，包括以阵列排列并具有浮体的多个晶体管，连接到晶体管的栅电极的字线，第一侧的位线连接到晶体管漏极的栅电极，栅电极的第二侧的源极线，不同于第一侧，并连接到半导体衬底上的晶体管的源极，以及栅电极与栅电极之间的电荷存储区域浮体。

5. 发明申请

US20080169501A1 FLASH MEMORY DEVICE WITH HYBRID STRUCTURE CHARGE TRAP LAYER AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：具有混合结构电荷捕获层的闪存存储器件及其制造方法
公开(公告)号：US20080169501A1
公开(公告)日：2008-07-17
申请号：US11776723
申请日：2007-07-12
申请人： Jun-kyu YANG , Seung-jae BAIK , Jin-tae NOH , Seung-hyun LIM , Kyong-hee JOO , Zong-liang HUO
发明人： Jun-kyu YANG , Seung-jae BAIK , Jin-tae NOH , Seung-hyun LIM , Kyong-hee JOO , Zong-liang HUO
IPC分类号： H01L29/788 , H01L21/3205
CPC分类号： H01L29/42332 , H01L29/40114 , H01L29/40117 , H01L29/42348 , H01L29/7881 , H01L29/792
摘要： A flash memory device including a hybrid structure charge trap layer and a related method of manufacture are disclosed. The charge trap layer includes at least one hybrid trap layer including a first trap layer formed from a first material having a first band gap energy, and a plurality of nano dots separated from each other such that each nano dot is at least partially encircled by the first trap layer, the plurality of nano dots being formed from a second material having a second band gap energy lower than the first band gap energy.
摘要翻译：公开了一种包括混合结构电荷陷阱层和相关制造方法的闪速存储器件。电荷陷阱层包括至少一个混合陷阱层，其包括由具有第一带隙能量的第一材料形成的第一陷阱层和彼此分离的多个纳米点，使得每个纳米点至少部分地被第一陷阱层，所述多个纳米点由具有低于第一带隙能量的第二带隙能量的第二材料形成。

6. 发明授权

US07368788B2 SRAM cells having inverters and access transistors therein with vertical fin-shaped active regions 失效
标题翻译：具有反相器和存取晶体管的SRAM单元具有垂直鳍状有源区
公开(公告)号：US07368788B2
公开(公告)日：2008-05-06
申请号：US11375617
申请日：2006-03-14
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/10 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/785
摘要： Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.
摘要翻译：互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）单元包括形成为具有相反导电类型的堆叠半导体区域的鳍状图案的至少第一反相器。在这些实施例的一些中，第一反相器包括与第二导电类型（例如，N型P型）MOS驱动器串联电耦合的第一导电类型（例如，P型或N型）MOS负载晶体管晶体管。第一反相器被布置成使得第一导电类型MOS负载晶体管和第二导电类型驱动晶体管的有源区在垂直双电导率半导体鳍结构的第一部分内相对于彼此垂直堆叠。这种翅片结构在至少三面被环绕的栅电极包围，该环形栅电极被配置成响应于栅极信号调制两个有源区的电导率。

7. 发明申请

US20060220134A1 CMOS SRAM cells employing multiple-gate transistors and methods fabricating the same 失效
标题翻译：采用多栅极晶体管的CMOS SRAM单元及其制造方法
公开(公告)号：US20060220134A1
公开(公告)日：2006-10-05
申请号：US11375617
申请日：2006-03-14
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/785
摘要： Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.
摘要翻译：互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）单元包括形成为具有相反导电类型的堆叠半导体区域的鳍状图案的至少第一反相器。在这些实施例的一些中，第一反相器包括与第二导电类型（例如，N型P型）MOS驱动器串联电耦合的第一导电类型（例如，P型或N型）MOS负载晶体管晶体管。第一反相器被布置成使得第一导电类型MOS负载晶体管和第二导电类型驱动晶体管的有源区在垂直双电导率半导体鳍结构的第一部分内相对于彼此垂直堆叠。这种翅片结构在至少三面被环绕的栅电极包围，该环形栅电极被配置成响应于栅极信号调制两个有源区的电导率。

8. 发明授权

US08405137B2 Single transistor floating-body DRAM devices having vertical channel transistor structures 失效
标题翻译：具有垂直沟道晶体管结构的单晶体管浮体DRAM器件
公开(公告)号：US08405137B2
公开(公告)日：2013-03-26
申请号：US13301254
申请日：2011-11-21
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L29/788
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.
摘要翻译：单晶体体浮体DRAM器件具有垂直沟道晶体管结构。 DRAM器件包括衬底，以及设置在衬底上并彼此隔离的第一和第二浮体。源极区域和漏极区域设置在第一和第二浮体的每一个之下和之上。栅电极设置在第一和第二浮体之间。还提供了制造单晶体管浮体DRAM器件的方法。

9. 发明授权

US08269268B2 Charge trap flash memory device and memory card and system including the same 有权
标题翻译：充电陷阱闪存设备和存储卡及系统包括相同
公开(公告)号：US08269268B2
公开(公告)日：2012-09-18
申请号：US12080315
申请日：2008-04-02
申请人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
发明人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7881
摘要： The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.
摘要翻译：该器件包括：隧道绝缘层，电荷陷阱层; 阻挡绝缘层; 以及依次形成在基板上的栅电极。电荷陷阱层包括：多个陷阱层，包括具有第一带隙能级的第一材料; 间隔开的纳米点，每个纳米点至少部分地被至少一个捕获层包围，其中该纳米点包括具有低于第一带隙能级的第二带隙能级的第二材料; 以及中间阻挡层，其包括形成在至少两个所述捕获层之间的具有高于所述第一带隙能级的第三带隙能级的第三材料。这种结构防止电荷陷阱层的电荷损失并且改善电荷存储容量。

10. 发明授权

US07795659B2 DRAM device and method of manufacturing the same 失效
标题翻译： DRAM装置及其制造方法
公开(公告)号：US07795659B2
公开(公告)日：2010-09-14
申请号：US12149406
申请日：2008-05-01
申请人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
发明人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10873 , H01L27/10829
摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.
摘要翻译：在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。非导电图案具有比导电图案的带隙大的带隙。在MTJ结构的侧壁上形成栅极绝缘层和栅电极。字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因此DRAM器件需要较小的衬底表面积。

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