专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07994493B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07994493B2
公开(公告)日：2011-08-09
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.
摘要翻译：相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

2. 发明申请

US20110053293A1 MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：US20110053293A1
公开(公告)日：2011-03-03
申请号：US12915335
申请日：2010-10-29
申请人： Woo-Yeong CHO , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong CHO , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L21/62
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

3. 发明申请

US20110002160A1 METHOD OF OPERATING A MAGNETORESISTIVE RAM 失效
标题翻译：操作磁记录RAM的方法
公开(公告)号：US20110002160A1
公开(公告)日：2011-01-06
申请号：US12875297
申请日：2010-09-03
申请人： Woo-yeong CHO , Yun-seung SHIN
发明人： Woo-yeong CHO , Yun-seung SHIN
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1655 , G11C11/1659 , Y10S977/935
摘要： A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
摘要翻译：磁阻随机存取存储器（RAM）可以包括多个可变电阻器件，电连接到相应的可变电阻器件的多个读位线以及与读位线交替的多个写位线。磁阻RAM可以被配置为当向第一可变电阻器件写入第一数据时，通过与第一可变电阻器件相邻的第一写入位线施加第一写入电流，并且将第一写入电流施加到与第一可写入位置相邻的第二写入位置第二可变电阻器件，第二可变电阻器件与第一写入位线相邻，第一写入位线和第二写入位线之间以及第一写入电流和第一抑制电流沿相同的方向流动。

4. 发明申请

US20090273045A1 MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：US20090273045A1
公开(公告)日：2009-11-05
申请号：US12507504
申请日：2009-07-22
申请人： Woo-Yeong CHO , Yun-Seung SHIN , Hyun-Geun BYUN , Choong-Keun KWAK
发明人： Woo-Yeong CHO , Yun-Seung SHIN , Hyun-Geun BYUN , Choong-Keun KWAK
IPC分类号： H01L29/82 , G11C11/14
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

5. 发明授权

US07573411B2 Digital-to-analog converter, display panel driver having the same, and digital-to-analog converting method 有权
标题翻译：数模转换器，具有相同功能的显示面板驱动器和数 - 模转换方法
公开(公告)号：US07573411B2
公开(公告)日：2009-08-11
申请号：US12007333
申请日：2008-01-09
申请人： Yun-seung Shin , Ju-hyun Ko
发明人： Yun-seung Shin , Ju-hyun Ko
IPC分类号： H03M1/68 , G09G5/10
CPC分类号： H03M1/667 , H03M1/662 , H03M1/682 , H03M1/765
摘要： A digital-to-analog converter outputting an analog data voltage corresponding to n-bit data, includes a chopping amplification unit adapted to receive an upper bit voltage corresponding to upper x bits of the n-bit data and a lower bit voltage corresponding to lower y bits of the n-bit data and to output the analog data voltage. The chopping amplification unit may include a sample and hold capacitor adapted to be charged with the upper bit voltage in a non-inverting mode, and a chopping amplifier adapted to supply the upper bit voltage to the sample and hold capacitor in the non-inverting mode and adapted to output a voltage corresponding to the sum of the upper bit voltage and the lower bit voltage as the analog data voltage in an inverting mode.
摘要翻译：输出对应于n位数据的模拟数据电压的数模转换器包括斩波放大单元，其适于接收对应于n位数据的高x位的高位电压和对应于低位的低位电压 y比特数据，并输出模拟数据电压。斩波放大单元可以包括适于以非反相模式对高位电压进行充电的采样和保持电容器，以及斩波放大器，其适于以非反相模式将采样和保持电容器提供高位电压并且适于在反相模式中输出对应于高位电压和低位电压之和的电压作为模拟数据电压。

6. 发明申请

US20080074917A1 Magnetoresistive RAM and associated methods 失效
标题翻译：磁阻RAM及相关方法
公开(公告)号：US20080074917A1
公开(公告)日：2008-03-27
申请号：US11902711
申请日：2007-09-25
申请人： Woo-yeong Cho , Yun-seung Shin
发明人： Woo-yeong Cho , Yun-seung Shin
IPC分类号： G11C11/02
CPC分类号： G11C11/1675 , G11C11/1655 , G11C11/1659 , Y10S977/935
摘要： A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
摘要翻译：磁阻随机存取存储器（RAM）可以包括多个可变电阻器件，电连接到相应的可变电阻器件的多个读位线以及与读位线交替的多个写位线。磁阻RAM可以被配置为当向第一可变电阻器件写入第一数据时，通过与第一可变电阻器件相邻的第一写入位线施加第一写入电流，并且将第一写入电流施加到与第一可写入位置相邻的第二写入位置第二可变电阻器件，第二可变电阻器件与第一写入位线相邻，第一写入位线和第二写入位线之间以及第一写入电流和第一抑制电流沿相同的方向流动。

7. 发明申请

US20060186483A1 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US20060186483A1
公开(公告)日：2006-08-24
申请号：US11324112
申请日：2005-12-30
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/76
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.
摘要翻译：提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体之间的间隙区域多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

8. 发明授权

US5965939A Semiconductor device and a method of manufacture 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5965939A
公开(公告)日：1999-10-12
申请号：US838044
申请日：1997-04-22
申请人： Kyeong-tae Kim , Yun-seung Shin , Young-hun Park , Won-mo Park , Ji-hong Ahn
发明人： Kyeong-tae Kim , Yun-seung Shin , Young-hun Park , Won-mo Park , Ji-hong Ahn
IPC分类号： H01L21/3205 , H01L21/3105 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L23/48
CPC分类号： H01L27/10808 , H01L21/31056 , H01L21/76819 , H01L27/105 , Y10S438/926
摘要： A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.
摘要翻译：提供一种半导体器件，其具有闭合台阶部分和包括在全局台阶部分上具有平坦化表面的绝缘层的全局阶跃部分。通过在全局台阶部分上形成绝缘层，然后通过光刻工艺进行图案化，形成虚拟图案。在形成用于补偿全局台阶部分之间和闭合台阶部分与全局台阶部分之间的步骤的虚拟图案之后，在封闭台阶部分和全局台阶部分上形成BPSG层，然后BPSG层被热封，处理以使其回流。作为具有平坦化表面的绝缘中间层的BPSG层。改进的平面化减少了随后的金属化处理中的开槽和不连续的发生，从而提高了半导体器件的产量和电特性。

9. 发明授权

US5019881A Nonvolatile semiconductor memory component 失效
标题翻译：非易失性半导体存储器组件
公开(公告)号：US5019881A
公开(公告)日：1991-05-28
申请号：US391865
申请日：1989-08-10
申请人： Yun-Seung Shin , Sung-Oh Chun
发明人： Yun-Seung Shin , Sung-Oh Chun
IPC分类号： G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7885
摘要： The invention provides a nonvolatile semiconductor memory component comprising: field region of thick oxide, the first and second active regions surrounded with the field region, the first and second gate insulating layers on the first and second active regions, the first gate of a low resistance formed on the first and second gate insulating layer, the third insulating layer on the first gate of a low resistance the second gate of a low resistance formed on the third insulating layer, the channel region below the first gate insulating layer formed by the first gate, and the highly doped drain and source separated by channel region opposite to the type of the substrate. In addition, the process for forming the transistor with one channel and the substrate diffusion can be achieved on the semiconductor substrate or opposite type well formed on the semiconductor substrate. Programming at a low voltage may be possible and the reliability characteristics of the cell may be improved according to present invention.
摘要翻译：本发明提供了一种非易失性半导体存储器组件，包括：厚氧化物的场区域，被场区域包围的第一和第二有源区域，第一和第二有源区域上的第一和第二栅极绝缘层，低电阻的第一栅极形成在所述第一和第二栅极绝缘层上，所述第一栅极上的所述第三绝缘层具有低电阻，形成在所述第三绝缘层上的低电阻的第二栅极，所述第一栅极绝缘层下方的所述沟道区域由所述第一栅极，并且高掺杂的漏极和源极通过与衬底类型相反的沟道区分离。此外，用于形成具有一个沟道的晶体管和衬底扩散的工艺可以在半导体衬底上或在半导体衬底上良好形成的相反类型上实现。根据本发明，可以以低电压进行编程，并且可以提高电池的可靠性特性。

10. 发明授权

US07952918B2 Method of operating a magnetoresistive RAM 失效
标题翻译：操作磁阻RAM的方法
公开(公告)号：US07952918B2
公开(公告)日：2011-05-31
申请号：US12875297
申请日：2010-09-03
申请人： Woo-yeong Cho , Yun-seung Shin
发明人： Woo-yeong Cho , Yun-seung Shin
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1655 , G11C11/1659 , Y10S977/935
摘要： A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
摘要翻译：磁阻随机存取存储器（RAM）可以包括多个可变电阻器件，电连接到相应的可变电阻器件的多个读位线以及与读位线交替的多个写位线。磁阻RAM可以被配置为当向第一可变电阻器件写入第一数据时，通过与第一可变电阻器件相邻的第一写入位线施加第一写入电流，并且将第一写入电流施加到与第一可写入位置相邻的第二写入位置第二可变电阻器件，第二可变电阻器件与第一写入位线相邻，第一写入位线和第二写入位线之间以及第一写入电流和第一抑制电流沿相同的方向流动。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式