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1. 发明授权

US07659167B2 Method for improving the performance of flash memory by using microcrystalline silicon film as a floating gate 有权
标题翻译：通过使用微晶硅膜作为浮动栅极来提高闪存性能的方法
公开(公告)号：US07659167B2
公开(公告)日：2010-02-09
申请号：US11422059
申请日：2006-06-02
申请人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
发明人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/4916 , H01L21/02532 , H01L21/02576 , H01L21/02595 , H01L21/0262 , H01L21/28273 , H01L29/42324
摘要： This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.
摘要翻译：本发明提供了一种通过使用硅烷引入氢来形成多晶硅的方法，使得多晶硅是微晶的。这种微晶多晶硅可以应用于闪存的浮动栅极，以提高闪存的性能。

2. 发明申请

US20080270056A1 WAFER-LEVEL RELIABILITY YIELD ENHANCEMENT SYSTEM AND RELATED METHOD 审中-公开
标题翻译：水平可靠性增强系统及相关方法
公开(公告)号：US20080270056A1
公开(公告)日：2008-10-30
申请号：US11740916
申请日：2007-04-26
申请人： Yun-Chi Yang , Cheng-Li Lin , Chia-Jen Kao , Ju-Ping Chen , Kuan-Cheng Su
发明人： Yun-Chi Yang , Cheng-Li Lin , Chia-Jen Kao , Ju-Ping Chen , Kuan-Cheng Su
IPC分类号： H01L21/66 , G01N37/00
CPC分类号： H01L22/20
摘要： A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.
摘要翻译：屈服增强系统具有制造线，其具有用于制造晶片的半导体制造装置，耦合到制造线的检查和测量监测系统，用于确定对应于半导体制造装置的工艺数据，以及耦合到制造线的后处理测试线用于进行在线晶圆级测试。后处理测试线包括晶片接收测试仪，耦合到晶片接收测试仪的屈服监测器，以及耦合到晶片接收测试仪的晶片级可靠性测试器，用于估计晶片上的器件的寿命。

3. 发明申请

US20050084990A1 Endpoint detection in manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件中的端点检测
公开(公告)号：US20050084990A1
公开(公告)日：2005-04-21
申请号：US10685484
申请日：2003-10-16
申请人： Yuh-Turng Liu , Kuang-Chao Chen , Hsueh-Hao Shih , Yun-Chi Yang , Yung-Tai Hung
发明人： Yuh-Turng Liu , Kuang-Chao Chen , Hsueh-Hao Shih , Yun-Chi Yang , Yung-Tai Hung
IPC分类号： G01R31/26 , H01L21/302 , H01L21/3105 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/66 , H01L21/768
CPC分类号： H01L21/31053 , H01L21/76819
摘要： A method of manufacturing a semiconductor device that comprises the steps of providing a semiconductor wafer including a patterned layer, forming a first insulating layer over the patterned layer of the semiconductor wafer, the first insulating layer including a first index of refraction, forming a second insulating layer over the first insulating layer, the second insulating layer including a second index of refraction smaller than the first index of refraction, removing the second insulating layer by a planarizing process, and detecting a change in index of refraction during the planarizing process.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：提供包括图案化层的半导体晶片，在半导体晶片的图案化层上形成第一绝缘层，第一绝缘层包括第一折射率，形成第二绝缘层第二绝缘层包括小于第一折射率的第二折射率，通过平坦化处理去除第二绝缘层，并且在平坦化处理期间检测折射率的变化。

4. 发明申请

US20120166130A1 METHOD FOR EVALUATING FAILURE RATE 有权
标题翻译：评估失败率的方法
公开(公告)号：US20120166130A1
公开(公告)日：2012-06-28
申请号：US12979914
申请日：2010-12-28
申请人： Yun-Chi YANG , Yen-Song Liu , Chin-Hsien Chen , Sheng-Yu Wu , Kuan-Cheng Su
发明人： Yun-Chi YANG , Yen-Song Liu , Chin-Hsien Chen , Sheng-Yu Wu , Kuan-Cheng Su
IPC分类号： G06F19/00
CPC分类号： G11C29/52 , G01R31/287 , G11C29/42 , G11C29/44 , G11C29/56008 , G11C2029/0409 , G11C2029/0411
摘要： A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.
摘要翻译：一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。每个半导体芯片的错误检查和校正功能关闭。对半导体芯片进行老化试验。作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

5. 发明授权

US07754611B2 Chemical mechanical polishing process 有权
标题翻译：化学机械抛光工艺
公开(公告)号：US07754611B2
公开(公告)日：2010-07-13
申请号：US11364482
申请日：2006-02-28
申请人： Chun Fu Chen , Yung Tal Hung , Yun Chi Yang
发明人： Chun Fu Chen , Yung Tal Hung , Yun Chi Yang
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , C09G1/02 , H01L21/02065
摘要： A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.
摘要翻译：公开了一种化学机械抛光方法。该方法包括在其上具有至少一个沟槽结构的晶片上形成膜; 通过提供抛光组合物来抛光膜的表面以提供第一抛光表面; 用漂洗组合物漂洗第一抛光表面以提供漂洗表面; 并通过提供第二抛光组合物来抛光冲洗的表面以提供第二抛光表面。

6. 发明授权

US07589551B1 On-wafer AC stress test circuit 有权
标题翻译：片上AC压力测试电路
公开(公告)号：US07589551B1
公开(公告)日：2009-09-15
申请号：US12107772
申请日：2008-04-23
申请人： Yun-Chi Yang , Chao-Yung Lai , Chao-Yang Lin , Cheng-Li Lin , Kuan-Cheng Su
发明人： Yun-Chi Yang , Chao-Yung Lai , Chao-Yang Lin , Cheng-Li Lin , Kuan-Cheng Su
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R31/2858 , G01R31/2884
摘要： To make an alternating current (AC) stress test easier to perform in a wafer, an AC stress test circuit for performing the AC stress test on a test device fabricated in a test region of the wafer includes an oscillator module fabricated in the test region, a diode module fabricated in the test region coupled to an output of the oscillator module, and a select transistor fabricated in the test region having a gate terminal coupled to an output of the diode module, a second terminal coupled to a gate of the test device, and a third terminal coupled to a test voltage source.
摘要翻译：为了在晶片中更容易进行交流（AC）应力测试，用于对在晶片的测试区域中制造的测试装置进行AC应力测试的AC应力测试电路包括在测试区域中制造的振荡器模块，制造在耦合到振荡器模块的输出的测试区域中的二极管模块，以及制造在测试区域中的选择晶体管，其具有耦合到二极管模块的输出的栅极端子，耦合到测试装置的栅极的第二端子以及耦合到测试电压源的第三端子。

7. 发明授权

US07544618B2 Two-step chemical mechanical polishing process 有权
标题翻译：两步化学机械抛光工艺
公开(公告)号：US07544618B2
公开(公告)日：2009-06-09
申请号：US11419129
申请日：2006-05-18
申请人： Chun-Fu Chen , Yung-Tai Hung , Chi-Tung Huang , Yun-Chi Yang
发明人： Chun-Fu Chen , Yung-Tai Hung , Chi-Tung Huang , Yun-Chi Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31053 , C09G1/02 , H01L22/12 , H01L22/20
摘要： A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.
摘要翻译：公开了一种化学机械抛光方法。该方法包括在其上具有至少一个沟槽结构的晶片上形成膜; 通过提供抛光组合物来抛光膜的表面以提供第一抛光表面; 用漂洗组合物漂洗第一抛光表面以提供漂洗表面; 并通过提供第二抛光组合物来抛光冲洗的表面以提供第二抛光表面。

8. 发明申请

US20070269985A1 TWO-STEP CHEMICAL MECHANICAL POLISHING PROCESS 有权
标题翻译：两步化学机械抛光工艺
公开(公告)号：US20070269985A1
公开(公告)日：2007-11-22
申请号：US11419129
申请日：2006-05-18
申请人： Chun-Fu Chen , Yung-Tai Hung , Chi-Tung Huang , Yun-Chi Yang
发明人： Chun-Fu Chen , Yung-Tai Hung , Chi-Tung Huang , Yun-Chi Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31053 , C09G1/02 , H01L22/12 , H01L22/20
摘要： A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.
摘要翻译：公开了一种化学机械抛光方法。该方法包括在其上具有至少一个沟槽结构的晶片上形成膜; 通过提供抛光组合物来抛光膜的表面以提供第一抛光表面; 用漂洗组合物漂洗第一抛光表面以提供漂洗表面; 并通过提供第二抛光组合物来抛光冲洗的表面以提供第二抛光表面。

9. 发明授权

US08510635B2 Method for evaluating failure rate 有权
标题翻译：评估失败率的方法
公开(公告)号：US08510635B2
公开(公告)日：2013-08-13
申请号：US12979914
申请日：2010-12-28
申请人： Yun-Chi Yang , Yen-Song Liu , Chin-Hsien Chen , Sheng-Yu Wu , Kuan-Cheng Su
发明人： Yun-Chi Yang , Yen-Song Liu , Chin-Hsien Chen , Sheng-Yu Wu , Kuan-Cheng Su
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G01R31/287 , G11C29/42 , G11C29/44 , G11C29/56008 , G11C2029/0409 , G11C2029/0411
摘要： A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.
摘要翻译：一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。每个半导体芯片的错误检查和校正功能关闭。对半导体芯片进行老化试验。作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

10. 发明申请

US20050037578A1 [METHOD FOR FORMING AN OXIDE/ NITRIDE/OXIDE STACKED LAYER] 审中-公开
标题翻译： [形成氧化物/氮化物/氧化物堆叠层的方法]
公开(公告)号：US20050037578A1
公开(公告)日：2005-02-17
申请号：US10604764
申请日：2003-08-14
申请人： Wei Wen Chen , Tzung-Ting Han , Yun-Chi Yang , Ling-Wuu Yang , Kuang-Chao Chen
发明人： Wei Wen Chen , Tzung-Ting Han , Yun-Chi Yang , Ling-Wuu Yang , Kuang-Chao Chen
IPC分类号： H01L21/28 , H01L21/314 , H01L21/336 , H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/0217 , H01L21/022 , H01L21/02332 , H01L21/3144 , H01L29/40114
摘要： A method for fabricating a silicon oxide/silicon nitride/silicon oxide stacked layer structure is described. A bottom oxide layer is formed over a substrate. A surface treatment is then performed on the first silicon oxide layer to form an interface layer over the bottom oxide layer. The surface treatment is conducted in a nitrogen ambient. Thereafter, a silicon nitride layer is formed over the interface layer, followed by forming an upper silicon oxide layer over the silicon nitride layer.
摘要翻译：描述了制造氧化硅/氮化硅/氧化硅堆叠层结构的方法。在衬底上形成底部氧化物层。然后对第一氧化硅层进行表面处理，以在底部氧化物层上形成界面层。表面处理在氮气环境中进行。此后，在界面层上形成氮化硅层，随后在氮化硅层上形成上部氧化硅层。

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