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1. 发明授权

US07659167B2 Method for improving the performance of flash memory by using microcrystalline silicon film as a floating gate 有权
标题翻译：通过使用微晶硅膜作为浮动栅极来提高闪存性能的方法
公开(公告)号：US07659167B2
公开(公告)日：2010-02-09
申请号：US11422059
申请日：2006-06-02
申请人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
发明人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/4916 , H01L21/02532 , H01L21/02576 , H01L21/02595 , H01L21/0262 , H01L21/28273 , H01L29/42324
摘要： This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.
摘要翻译：本发明提供了一种通过使用硅烷引入氢来形成多晶硅的方法，使得多晶硅是微晶的。这种微晶多晶硅可以应用于闪存的浮动栅极，以提高闪存的性能。

2. 发明授权

US07341910B2 Method for forming a flash memory by using a microcrystalline polysilicon layer as a floating gate 有权
标题翻译：通过使用微晶多晶硅层作为浮动栅极形成闪速存储器的方法
公开(公告)号：US07341910B2
公开(公告)日：2008-03-11
申请号：US10192565
申请日：2002-07-11
申请人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
发明人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/4916 , H01L21/02532 , H01L21/02576 , H01L21/02595 , H01L21/0262 , H01L21/28273 , H01L29/42324
摘要： This invention provides a method for forming a microcrystalline polysilicon layer by using silane or dislane with introducing hydrogen gas. This microcrystalline polysilicon layer can be used as a floating gate of a flash memory to improve the character of the flash memory.
摘要翻译：本发明提供一种通过使用硅烷或二异氰酸酯引入氢气来形成微晶多晶硅层的方法。该微晶多晶硅层可以用作闪存的浮动栅极以改善闪存的特性。

3. 发明授权

US06624023B1 Method for improving the performance of flash memory 有权
标题翻译：提高闪存性能的方法
公开(公告)号：US06624023B1
公开(公告)日：2003-09-23
申请号：US10152585
申请日：2002-05-23
申请人： Tzung-Ting Han , Chun-Lein Su , Chin-Ta Su
发明人： Tzung-Ting Han , Chun-Lein Su , Chin-Ta Su
IPC分类号： H01L21336
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/954
摘要： The method for improving the performance of flash memory. A substrate is proved. A tunnel oxide layer is formed on the substrate. There two gate, structure are formed on the tunnel oxide layer. The gate structure including a first polysilicon layer as a floating gate, an interpoly dielectric layer such as ONO layer on the floating gate, a second polysilicon layer as a control gate on the interpoly dielectric layer. Moreover, the poly stringer is exit between the gates, wherein the poly stringer is unmovied after etched. Next, the oxygen free radical process cell oxidation is processed. The results ONO encroachment is very slightly then improvement of 6% GCR with pre-mixing gas process cell oxidation can increase operation speed by more than 5 times and eliminated poly stringer.
摘要翻译：提高闪存性能的方法。证明了底物。在衬底上形成隧道氧化物层。在隧道氧化层上形成两个门，结构。栅极结构包括作为浮置栅极的第一多晶硅层，浮置栅极上的诸如ONO层的多晶硅间介质层，作为在多晶硅间介电层上的控制栅极的第二多晶硅层。此外，多晶硅在栅极之间离开，其中多晶硅在蚀刻后不被剥离。接下来，处理氧自由基过程电池氧化。结果ONO侵蚀非常轻微，然后改进6％GCR，预混合气体处理池氧化可以将操作速度提高5倍以上，消除多边形。

4. 发明申请

US20140015107A1 METHOD TO IMPROVE WITHIN WAFER UNIFORMITY OF CMP PROCESS 审中-公开
标题翻译：在CMP工艺的WAFER均匀性中改进的方法
公开(公告)号：US20140015107A1
公开(公告)日：2014-01-16
申请号：US13547333
申请日：2012-07-12
申请人： Ching-Kun Chen , Chun-Fu Chen , Chin-Ta Su
发明人： Ching-Kun Chen , Chun-Fu Chen , Chin-Ta Su
IPC分类号： B24B49/14 , H01L29/06 , H01L21/306 , B24B49/02 , B24D3/00
CPC分类号： B24B37/015 , H01L21/3212 , H01L22/12 , H01L22/26
摘要： Closed loop control may be used to improve uniformity of within wafer uniformity using chemical mechanical planarization. For example, closed loop control may be used to determine a control profile for a chemical mechanical planarization process to more uniformly and consistently achieve the desired extent of variation of within wafer uniformity of a semiconductor wafer.
摘要翻译：可以使用闭环控制来提高使用化学机械平面化的晶片均匀性的均匀性。例如，可以使用闭环控制来确定用于化学机械平面化工艺的控制曲线，以更均匀且一致地实现半导体晶片的晶圆内均匀度期望的变化范围。

5. 发明申请

US20130241075A1 CONTACT OR VIA CRITICAL DIMENSION CONTROL WITH NOVEL CLOSED LOOP CONTROL SYSTEM IN CHEMICAL MECHANICAL PLANARIZATION PROCESS 审中-公开
标题翻译：联系或通过化学机械平面化过程中的新型闭环控制系统的关键尺寸控制
公开(公告)号：US20130241075A1
公开(公告)日：2013-09-19
申请号：US13418920
申请日：2012-03-13
申请人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
发明人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
IPC分类号： H01L21/306 , H01L29/30 , B24B49/00
CPC分类号： B24B37/013 , H01L21/3212 , H01L21/7684 , H01L22/12 , H01L22/20
摘要： Closed loop control may be used to improve uniformity of contact or via critical dimension using chemical mechanical planarization. For example, real-time closed loop control may be used to adjust oxide buffing or over-polishing time in a chemical mechanical planarization process to more uniformly and consistently achieve a target critical dimension of a semiconductor wafer.
摘要翻译：闭环控制可用于通过化学机械平面化改善接触的均匀性或通过临界尺寸。例如，实时闭环控制可用于在化学机械平面化工艺中调节氧化物抛光或过抛光时间，以更均匀且一致地实现半导体晶片的目标临界尺寸。

6. 发明授权

US08085390B2 Multivariate monitoring method for plasma process machine 有权
标题翻译：等离子体处理机多变量监测方法
公开(公告)号：US08085390B2
公开(公告)日：2011-12-27
申请号：US11737541
申请日：2007-04-19
申请人： Tuung Luoh , Shing-Ann Luo , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Shing-Ann Luo , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： G01N21/00
CPC分类号： G01N21/68 , H01J37/32935 , H01J37/32972
摘要： An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.
摘要翻译：提供了一种用于等离子体处理机的先进过程控制（APC）系统，其包括至少一个光发射光谱（OES）系统和APC分析装置。 OES系统用于监测等离子体处理机中的测试对象。 APC分析装置用于分析从OES系统接收到的数据。

7. 发明授权

US08047899B2 Pad and method for chemical mechanical polishing 有权
标题翻译：化学机械抛光垫和方法
公开(公告)号：US08047899B2
公开(公告)日：2011-11-01
申请号：US11878654
申请日：2007-07-26
申请人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
发明人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
IPC分类号： B24B7/22 , B24D3/34
CPC分类号： B24B37/24 , B24D3/346
摘要： A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.
摘要翻译：提供了半导体器件的两个相邻结构的化学机械抛光方法。一种用于机械抛光的方法，包括：（a）提供半导体器件，其包括在其表面形成的凹部，形成在所述表面上的第一层，以及填充有所述凹部并形成在所述第一层上的第二层; 和（b）用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层，其中该垫包括第二层的腐蚀抑制剂。

8. 发明授权

US07846835B2 Contact barrier layer deposition process 有权
标题翻译：接触阻挡层沉积工艺
公开(公告)号：US07846835B2
公开(公告)日：2010-12-07
申请号：US11950319
申请日：2007-12-04
申请人： Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76841 , H01L21/2855 , H01L21/28556
摘要： A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium atoms from the titanium target with the gaseous ions, ionizing the titanium atoms using a plasma, and depositing the ionized titanium atoms onto the substrate to form the layer of Ti. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition (MOCVD) process. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process. The newly completed barrier layer is annealed in the presence of nitrogen at a temperature of between about 500° C. to about 750° C.
摘要翻译：公开了一种在衬底上沉积阻挡层的方法。使用电离金属等离子体（IMP）物理气相沉积工艺将一层钛（Ti）沉积到衬底上。 IMP过程包括：产生气体离子，将气态离子加速到钛靶，用钛离子溅射钛原子与气态离子，使用等离子体离子化钛原子，并将离子化的钛原子沉积到基底上形成 Ti层。使用金属有机化学气相沉积（MOCVD）工艺将第一层氮化钛（TiN）沉积到Ti层上。使用热化学气相沉积工艺将第二层TiN沉积到第一TiN层上。将新完成的阻挡层在氮气存在下在约500℃至约750℃的温度下进行退火。

9. 发明申请

US20090299668A1 APC SYSTEM AND MULTIVARIATE MONITORING METHOD FOR PLASMA PROCESS MACHINE 有权
公开(公告)号：US20090299668A1
公开(公告)日：2009-12-03
申请号：US12540001
申请日：2009-08-12
申请人： Tuung Luoh , Sheng-Hui Hsieh , Shing-Ann Luo , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Sheng-Hui Hsieh , Shing-Ann Luo , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： G06F19/00 , G06F15/00 , G01J3/30
CPC分类号： H01J37/32972 , G01N21/68 , H01J37/32935
摘要： An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.

10. 发明申请

US20080299761A1 Interconnection process 有权
标题翻译：互连过程
公开(公告)号：US20080299761A1
公开(公告)日：2008-12-04
申请号：US11806541
申请日：2007-06-01
申请人： Tuung Luoh , Ling-Wuu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ling-Wuu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/28518 , H01L21/76828
摘要： An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.
摘要翻译：提供互连过程。该过程包括以下步骤。首先，设置至少具有导电区域的半导体基板。接下来，形成具有接触孔的电介质层以覆盖半导体基底，其中接触孔暴露部分导电区域。然后，对覆盖有电介质层的半导体基板进行热处理。最后，在电介质层上形成导电层，其中导电层通过接触孔与导电区电连接。

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