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1. 发明专利

GB1473469A VOLTAGE LEVEL CHANGING CIRCUITS 未知
公开(公告)号：GB1473469A
公开(公告)日：1977-05-11
申请号：GB2159875
申请日：1975-05-20
申请人： IBM
IPC分类号： H03K19/0185 , H03K1/10
摘要： 1473469 Transistor level shifting circuits INTERNATIONAL BUSINESS MACHINES CORP 20 May 1975 [5 Aug 1974] 21598/75 Heading H3T In a circuit for producing an output signal of one or other of two output levels depending on the level of an input signal, a complementary pair of output FET's T7, T8 are connected in series across supply terminals and have their common junction connected to the output, a further complementary pair of FET's T5, T6 connected across the supply terminals and having their common junction connected to the gates of the output FET's T7, T8, and two complementary input FET's T1, T2 connected between an input terminal 1 and the gates of the FET's T5, T6. The gates of the additional FET's T1, T2 are connected to the output. When a substantial change in the input occurs, the appropriate one of the input FET's T1 or T2 is turned on so as to change the state of the latch comprising FET's T3 ... T6 and hence of the output. The change in output is fed back to the input FET T1 or T2 so that further change in output (e.g. due to noise) is inhibited by the large substrate reverse bias on T1 or T2.

3. 发明授权

US4016434A Load gate compensator circuit 失效
标题翻译：负载门补偿电路
公开(公告)号：US4016434A
公开(公告)日：1977-04-05
申请号：US610202
申请日：1975-09-04
申请人： Robert Joseph DeFilippi
发明人： Robert Joseph DeFilippi
IPC分类号： H03F1/30 , H01L21/8236 , H01L27/088 , H03K3/011 , H03K17/14 , H03K17/687 , H03K19/0944 , H03L1/00 , H03K1/02 , H03K1/10 , H03K19/08 , H03K19/40
CPC分类号： H03K17/145 , H03K3/011 , H03L1/00
摘要： An FET load gate compensator circuit is disclosed which compensates for variations in the parameters characterizing the silicon substrate in FET large scale integrated circuit device, by generating a compensatory load gate voltage to be applied to the load gates of the functional circuits therein.
摘要翻译：公开了一种FET负载栅补偿器电路，其通过产生施加到其中的功能电路的负载栅极的补偿性负载栅极电压来补偿表征FET大规模集成电路器件中的硅衬底的参数的变化。

4. 发明授权

US3513334A Circuit for suppressing undesirable a.c. signals superimposed on the power supply voltage 失效
标题翻译：用于抑制电源电压超级的不可接收的交流信号的电路
公开(公告)号：US3513334A
公开(公告)日：1970-05-19
申请号：US3513334D
申请日：1966-12-05
申请人： ELECTRONIC COMMUNICATIONS
发明人： BRUNNER ARTHUR C , HEINRICH ERIC C
IPC分类号： H02M1/15 , H03F1/30 , H03K1/02 , H03K1/10
CPC分类号： H02M1/15 , H03F1/302

5. 发明授权

US3440448A Generator for producing symmetrical triangular waves of variable repetition rate 失效
标题翻译：生成可变重复率对称三角波的发电机
公开(公告)号：US3440448A
公开(公告)日：1969-04-22
申请号：US3440448D
申请日：1965-11-01
申请人： HEWLETT PACKARD CO
发明人： DUDLEY ROBERT L
IPC分类号： H03K4/06 , H03K1/10
CPC分类号： H03K4/066

8. 发明专利

GB1441025A METHOD FOR PRODUCING INTERFERENCE-FREE PULSES AND AN ARRANGEMENT FOR CARRYING OUT THE METHOD 未知
公开(公告)号：GB1441025A
公开(公告)日：1976-06-30
申请号：GB5166873
申请日：1973-11-07
申请人： HARTIG G
IPC分类号： F02P7/067 , F02P15/00 , G01P3/48 , G01P3/481 , G01P3/484 , H03K3/013 , H03K3/02 , H03K3/45 , H03K3/64 , H03K1/10
摘要： The invention is concerned with producing interference-free (square) pulses with clean leading and trailing edges, from a pulse generator subject to vibration. This is effected by producing two interference-affected pulse trains of the same frequency but different phase, and applying them to a back-coupled gate circuit the output of which is turned "on" by the first interfering pulse of a first pulse train corresponding in time to an interference-free region of the second pulse train, and stays "on" until the end of the said interference free region, irrespective of any further interference in the first pulse sequence. The action is also repeated in reverse.

10. 发明专利

GB1372856A SAW TOOTH GENERATORS 未知
公开(公告)号：GB1372856A
公开(公告)日：1974-11-06
申请号：GB5768971
申请日：1971-12-11
申请人： MATSUSHITA ELECTRIC IND CO LTD
IPC分类号： H03K4/71 , H03K4/72 , H03K1/10 , H03K4/76
摘要： 1372856 Vertical deflection circuits MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 11 Dec 1971 57689/71 Heading H3T A vertical deflection circuit of the type comprising an integrator reset by a switching circuit and in which the switching circuit is operated by a narrow pulse from an oscillator synchronized by synchronizing pulses, positive feedback in the deflection circuit provides a pulse which maintains the switching circuit operated throughout the flyback period so that jitter due to variation in pulse width from the oscillator is avoided. The Figure shows a Miller integrator comprising transistors 55-59 and a feedback capacitance 63, 64, the integrator being charged through a resistor 73 and discharged through a transistor 53 in response to a synchronizing pulse received from an oscillator 52 via an isolating diode 54. Lineaity is improved by resistors 66 and 67 and a capacitor 68 prevents oscillation. A positive feedback pulse derived from the differentiating and attenuating circuit 41-44 maintains the switching transistor 5 conductive throughout the flyback. A capacitor 62 tunes the deflection coils.

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