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    • 5. 发明授权
    • Methods of forming multi-level cell of semiconductor memory
    • 形成半导体存储器多级单元的方法
    • US08187918B2
    • 2012-05-29
    • US12587772
    • 2009-10-13
    • Gyu-Hwan OhHyeung-Geun AnSoon-Oh ParkDong-Ho AhnYoung-Lim Park
    • Gyu-Hwan OhHyeung-Geun AnSoon-Oh ParkDong-Ho AhnYoung-Lim Park
    • H01L21/06
    • H01L45/141H01L27/2409H01L45/06H01L45/1233H01L45/1253H01L45/144H01L45/1666H01L45/1683
    • Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.
    • 提供了一种形成半导体存储单元的方法,其中为了在存储单元中存储两个或更多个数据,三个或更多个底部电极触点(BEC)和相变材料(GST)在单个存储单元上具有并联结构 接触插头(CP)和设定电阻根据三个或更多个底部电极触点的厚度(S),长度(L)或电阻率(&rgr)而改变,因此复位电阻和三种不同的设定电阻使数据不能 在设置和复位状态下存储。 此外,形成其中三个或更多个相变材料(GST)在单个底部电极接触上具有平行结构的存储单元的方法,并且相变材料根据组成比或类型具有不同的设定电阻,因此 可以实现四个或更多个不同的电阻。