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1. 发明授权

US09768255B2 Semiconductor devices including contact structures that partially overlap silicide layers 有权
公开(公告)号：US09768255B2
公开(公告)日：2017-09-19
申请号：US15006717
申请日：2016-01-26
申请人： Do-Sun Lee , Chang-Woo Sohn , Chul-Sung Kim , Shigenobu Maeda , Young-Moon Choi , Hyo-Seok Choi , Sang-Jin Hyun
发明人： Do-Sun Lee , Chang-Woo Sohn , Chul-Sung Kim , Shigenobu Maeda , Young-Moon Choi , Hyo-Seok Choi , Sang-Jin Hyun
IPC分类号： H01L29/08 , H01L29/06 , H01L29/161 , H01L29/165 , H01L29/78 , H01L29/417
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/7848 , H01L29/785
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

2. 发明申请

US20160308004A1 SEMICONDUCTOR DEVICES INCLUDING CONTACT STRUCTURES THAT PARTIALLY OVERLAP SILICIDE LAYERS 有权
标题翻译：半导体器件，包括部分覆盖硅化物层的接触结构
公开(公告)号：US20160308004A1
公开(公告)日：2016-10-20
申请号：US15006717
申请日：2016-01-26
申请人： Do-Sun LEE , Chang-Woo SOHN , Chul-Sung KIM , Shigenobu MAEDA , Young-Moon CHOI , Hyo-Seok CHOI , Sang-Jin HYUN
发明人： Do-Sun LEE , Chang-Woo SOHN , Chul-Sung KIM , Shigenobu MAEDA , Young-Moon CHOI , Hyo-Seok CHOI , Sang-Jin HYUN
IPC分类号： H01L29/08 , H01L29/165 , H01L29/161 , H01L29/78 , H01L29/06
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/7848 , H01L29/785
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.
摘要翻译：提供半导体器件。半导体器件包括衬底。半导体器件包括限定基板的有效部分的隔离层，其在一个方向上彼此间隔开。半导体器件在有源部分上包括外延层。半导体器件在外延层上包括金属硅化物层。此外，半导体器件包括仅在外延层上部分地重叠金属硅化物层的接触结构。还提供了形成半导体器件的相关方法。

3. 发明申请

US20130206202A1 SOLAR CELL 审中-公开
标题翻译：太阳能电池
公开(公告)号：US20130206202A1
公开(公告)日：2013-08-15
申请号：US13484902
申请日：2012-05-31
申请人： Yeon il Lee , Dong Kyun Kim , Yun Gi Kim , Chul Ki Kim , Eun Cheol Do , Young Moon Choi
发明人： Yeon il Lee , Dong Kyun Kim , Yun Gi Kim , Chul Ki Kim , Eun Cheol Do , Young Moon Choi
IPC分类号： H01L31/0216 , H01L31/042 , H01L31/0232
CPC分类号： H01L31/055 , H01L31/049 , H01L31/0543 , H01L31/056 , Y02E10/52
摘要： According to example embodiments, a solar cell includes a photoelectric member on a passivation member. The photoelectric member is configured to convert incident light into current. The passivation member includes protection material for protecting the-photoelectric member and wavelength conversion material configured to convert light that passes through the photoelectric member into different wavelength.
摘要翻译：根据示例性实施例，太阳能电池在钝化部件上包括光电部件。光电部件被配置为将入射光转换为电流。钝化部件包括用于保护光电元件和波长转换材料的保护材料，该材料被配置为将通过光电元件的光转换成不同的波长。

4. 发明授权

US08361905B2 Methods of forming patterns for semiconductor devices 有权
标题翻译：形成半导体器件图形的方法
公开(公告)号：US08361905B2
公开(公告)日：2013-01-29
申请号：US12581298
申请日：2009-10-19
申请人： Bong-cheol Kim , Dae-youp Lee , Hyun-woo Kim , Young-moon Choi , Jong-su Park , Byeong-hwan Son
发明人： Bong-cheol Kim , Dae-youp Lee , Hyun-woo Kim , Young-moon Choi , Jong-su Park , Byeong-hwan Son
IPC分类号： H01L21/302 , H01L21/461 , H01L21/311
CPC分类号： H01L21/76229 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526
摘要： Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern. First spacers covering side walls of the first mask pattern and second spacers covering side walls of the second mask pattern are formed. The first mask pattern is removed, and then the substrate is etched in the first region and the second region by using the first spacers as an etch mask in the first region, and the second mask pattern and the second spacers as an etch mask in the second region.
摘要翻译：提供了形成半导体器件的图案的方法，由此可以同时形成具有各种宽度的图案，并且在半导体器件的一部分中通过双重图案化工艺可以使图案密度加倍。在基板上形成双掩模层。在双掩模层上形成可变掩模层。在第一区域中具有第一厚度和第一宽度的第一光致抗蚀剂图案和具有大于第一厚度的第二厚度的第二光致抗蚀剂图案和宽于第二区域中的第一宽度的第二宽度形成在可变掩模层。在第一区域中形成第一掩模图案和第一可变掩模图案，并且通过使用可变掩模层和双掩模层依次蚀刻第二区域中的第二掩模图案和第二可变掩模图案，作为蚀刻掩模，第一光致抗蚀剂图案和第二光致抗蚀剂图案。形成覆盖第一掩模图案的侧壁的第一间隔物和覆盖第二掩模图案的侧壁的第二间隔物。去除第一掩模图案，然后通过在第一区域中使用第一间隔物作为蚀刻掩模在第一区域和第二区域中蚀刻衬底，并且在第二区域中将第二掩模图案和第二间隔物作为蚀刻掩模第二区。

5. 发明申请

US20120266933A1 SOLAR CELL 审中-公开
标题翻译：太阳能电池
公开(公告)号：US20120266933A1
公开(公告)日：2012-10-25
申请号：US13451784
申请日：2012-04-20
申请人： Eun Cheol Do , Dong Kyun Kim , Yun Gi Kim , Deok-Kee Kim , Young Moon Choi
发明人： Eun Cheol Do , Dong Kyun Kim , Yun Gi Kim , Deok-Kee Kim , Young Moon Choi
IPC分类号： H01L31/042
CPC分类号： H01L31/043 , Y02E10/50
摘要： According to example embodiments, a solar cell includes a first unit portion, a second unit portion, and an insulating layer. The first and second unit portions may have different bandgaps, and the insulating layer may be between the first unit portion and the second unit portion.
摘要翻译：根据示例性实施例，太阳能电池包括第一单元部分，第二单元部分和绝缘层。第一和第二单元部分可以具有不同的带隙，并且绝缘层可以在第一单元部分和第二单元部分之间。

6. 发明授权

US07982318B2 Device including contact structure and method of forming the same 失效
标题翻译：包括接触结构的装置及其形成方法
公开(公告)号：US07982318B2
公开(公告)日：2011-07-19
申请号：US11655116
申请日：2007-01-19
申请人： Jang-Eun Heo , Young-Moon Choi , Sun-Woo Lee , Hong-Sik Yoon , Kyung-Rae Byun
发明人： Jang-Eun Heo , Young-Moon Choi , Sun-Woo Lee , Hong-Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/3212 , H01L21/76823 , H01L21/76825 , H01L21/76831 , H01L21/76867 , H01L21/76876 , H01L21/76879 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , H01L2924/00
摘要： A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.
摘要翻译：一种器件包括在具有下导电图案的衬底上的绝缘层，所述绝缘层具有穿透绝缘层并暴露一部分下导电图案的接触孔，催化图案具有第一部分在暴露部分上下导电图案和接触孔的侧壁上的第二部分，在接触孔的侧壁上的间隔件，其中催化剂图案的第二部分设置在间隔件和侧壁之间，接触插塞在接触孔中并使催化剂图案接触，所述接触塞是碳纳米管材料。

7. 发明申请

US20100240221A1 Methods of Forming Patterns for Semiconductor Devices 有权
标题翻译：半导体器件形成模式的方法
公开(公告)号：US20100240221A1
公开(公告)日：2010-09-23
申请号：US12581298
申请日：2009-10-19
申请人： Bong-cheol Kim , Dae-youp Lee , Hyun-Woo Kim , Young-moon Choi , Jong-su Park , Byeong-hwan Son
发明人： Bong-cheol Kim , Dae-youp Lee , Hyun-Woo Kim , Young-moon Choi , Jong-su Park , Byeong-hwan Son
IPC分类号： H01L21/306
CPC分类号： H01L21/76229 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526
摘要： Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern. First spacers covering side walls of the first mask pattern and second spacers covering side walls of the second mask pattern are formed. The first mask pattern is removed, and then the substrate is etched in the first region and the second region by using the first spacers as an etch mask in the first region, and the second mask pattern and the second spacers as an etch mask in the second region.
摘要翻译：提供了形成半导体器件的图案的方法，由此可以同时形成具有各种宽度的图案，并且在半导体器件的一部分中通过双重图案化工艺可以使图案密度加倍。在基板上形成双掩模层。在双掩模层上形成可变掩模层。在第一区域中具有第一厚度和第一宽度的第一光致抗蚀剂图案和具有大于第一厚度的第二厚度的第二光致抗蚀剂图案和宽于第二区域中的第一宽度的第二宽度形成在可变掩模层。在第一区域中形成第一掩模图案和第一可变掩模图案，并且通过使用可变掩模层和双掩模层依次蚀刻第二区域中的第二掩模图案和第二可变掩模图案，作为蚀刻掩模，第一光致抗蚀剂图案和第二光致抗蚀剂图案。形成覆盖第一掩模图案的侧壁的第一间隔物和覆盖第二掩模图案的侧壁的第二间隔物。去除第一掩模图案，然后通过在第一区域中使用第一间隔物作为蚀刻掩模在第一区域和第二区域中蚀刻衬底，并且在第二区域中将第二掩模图案和第二间隔物作为蚀刻掩模第二区。

8. 发明申请

US20080135908A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080135908A1
公开(公告)日：2008-06-12
申请号：US11980355
申请日：2007-10-31
申请人： Young-moon Choi , Ji-young Kim , In-seok Yeo , Sun-woo Lee
发明人： Young-moon Choi , Ji-young Kim , In-seok Yeo , Sun-woo Lee
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/91 , B82Y10/00 , H01L27/10817 , H01L27/10852 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/41725 , Y10S977/742 , Y10S977/762 , Y10S977/766
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.
摘要翻译：提供半导体器件和制造半导体器件的方法，例如，使用碳纳米管或纳米线作为电容器的下电极的半导体器件，以及制造半导体器件的方法。半导体器件可以包括在半导体衬底上包括多个管或导线的下电极，下电极表面上的电介质层和介电层表面上的上电极，其中多个管或电线以多个管或线的下部为中心彼此向外辐射。因此，可以通过增加电容器的下电极的表面积来增加电容器的截止电流。

9. 发明授权

US07550791B2 Transistor and its method of manufacture 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US07550791B2
公开(公告)日：2009-06-23
申请号：US11832592
申请日：2007-08-01
申请人： Hong-Sik Yoon , Young-Moon Choi , Sun-Woo Lee
发明人： Hong-Sik Yoon , Young-Moon Choi , Sun-Woo Lee
IPC分类号： H01L21/336 , H01L21/335 , H01L29/786 , H01L29/06
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10T29/49105
摘要： An embodiment includes a transistor and a method of manufacturing the transistor that includes carbon nano-tubes. The physical behavior of the carbon nano-tubes, particularly a bending action that alters a normally linear configuration, is affected by elements of the transistor, such as a space between the carbon nano-tube and a conductor. The space is formed by removing a spacer. A dimension of the spacer between the carbon nano-tube and the conductor is efficiently controlled by adjusting its width. An operation voltage of the transistor relates to the physical behavior of the carbon nano-tubes, and thus to the dimensions of the spacer.
摘要翻译：实施例包括晶体管和制造包括碳纳米管的晶体管的方法。碳纳米管的物理行为，特别是改变正常线性构型的弯曲作用，受到晶体管的元件（例如碳纳米管和导体之间的空间）的影响。通过去除间隔物形成空间。通过调整碳纳米管和导体之间的间隔物的尺寸可有效地控制其宽度。晶体管的工作电压与碳纳米管的物理性能有关，因此与间隔物的尺寸有关。

10. 发明申请

US20080175984A1 METHOD OF FORMING A CARBON NANO-TUBE 有权
标题翻译：形成碳纳米管的方法
公开(公告)号：US20080175984A1
公开(公告)日：2008-07-24
申请号：US11832601
申请日：2007-08-01
申请人： Hong-Sik YOON , Young-Moon CHOI , Sun-Woo LEE
发明人： Hong-Sik YOON , Young-Moon CHOI , Sun-Woo LEE
IPC分类号： B05D5/12
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162 , Y10S977/742
摘要： In a method of forming carbon nano-tubes, a catalytic film is formed on a substrate. The catalytic film is then transformed into preliminary catalytic particles. Thereafter, the preliminary catalytic particles are transformed into catalytic particles. Carbon nano-tubes then grow from the catalytic particles. The carbon nano-tubes have relatively high conductivity and high number density.
摘要翻译：在形成碳纳米管的方法中，在基板上形成催化膜。然后将催化膜转化成预催化颗粒。此后，将预催化剂颗粒转化成催化剂颗粒。碳纳米管然后从催化颗粒生长。碳纳米管具有较高的导电性和高密度。

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