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1. 发明授权

US08754489B2 Ultrasonic transducer and manufacturing method 有权
标题翻译：超声波换能器及制造方法
公开(公告)号：US08754489B2
公开(公告)日：2014-06-17
申请号：US13605340
申请日：2012-09-06
申请人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
发明人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
IPC分类号： H01L27/14
CPC分类号： B06B1/0292 , Y10T29/49005
摘要： An ultrasonic transducer includes a first electrode, a first insulation film covering the first electrode, a hollow part overlapping the first electrode on the first insulation film, a second insulation film covering the hollow part, a second electrode overlapping the hollow part on the second insulation film, and an interconnection joined to the second electrode. An edge of the first electrode is formed so as to moderate a step of the first electrode.
摘要翻译：超声波换能器包括第一电极，覆盖第一电极的第一绝缘膜，与第一绝缘膜上的第一电极重叠的中空部分，覆盖中空部分的第二绝缘膜，与第二绝缘体上的中空部分重叠的第二电极膜，以及与第二电极接合的互连。形成第一电极的边缘以调节第一电极的台阶。

2. 发明申请

US20100148594A1 Ultrasonic Transducer And Manufacturing Method Thereof 有权
标题翻译：超声波传感器及其制造方法
公开(公告)号：US20100148594A1
公开(公告)日：2010-06-17
申请号：US12714631
申请日：2010-03-01
申请人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki , Tatsuya Nagata
发明人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki , Tatsuya Nagata
IPC分类号： H02N11/00
CPC分类号： B06B1/0292
摘要： An ultrasonic transducer includes a first electrode, a second electrode, an insulating film disposed between the first and second electrodes, and a cavity disposed between the first and second electrodes. The insulating film includes a projection extending in the cavity, and a portion of the cavity is disposed between the projection and the first electrode. A portion of one of the first electrode and the second electrode has an opening corresponding to a position of the projection of the insulating film when viewed in plan view.
摘要翻译：超声换能器包括第一电极，第二电极，设置在第一和第二电极之间的绝缘膜，以及设置在第一和第二电极之间的空腔。绝缘膜包括在空腔中延伸的突起，并且空腔的一部分设置在突起和第一电极之间。当在平面图中观察时，第一电极和第二电极中的一个的一部分具有对应于绝缘膜的突起的位置的开口。

3. 发明申请

US20080042225A1 ULTRASONIC TRANSDUCER AND MANUFACTURING METHOD 有权
标题翻译：超声波传感器和制造方法
公开(公告)号：US20080042225A1
公开(公告)日：2008-02-21
申请号：US11671040
申请日：2007-02-05
申请人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
发明人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
IPC分类号： H01L29/84 , H01L21/62
CPC分类号： B06B1/0292 , Y10T29/49005
摘要： This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.
摘要翻译：本发明提供一种技术，即使通过将下部电极分割成成分元件而产生台阶，也能够降低上部电极的电阻增加，膜的损伤以及上部电极与下部电极之间的介电强度的降低。在包括多个下电极的超声波换能器中，覆盖下电极的绝缘膜，形成为与绝缘膜上的下电极重叠的多个中空部，填充中空部之间的间隙的绝缘膜，覆盖中空部的绝缘膜，绝缘膜，形成为与绝缘膜上的中空部分重叠的多个上电极和连接它们的多个互连，中空部分和绝缘膜的表面被平坦化到相同的高度。

4. 发明授权

US06753219B2 Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices 有权
标题翻译：具有具有降低的位线杂散容量的存储器件的半导体集成电路器件的制造方法以及这种半导体集成电路器件
公开(公告)号：US06753219B2
公开(公告)日：2004-06-22
申请号：US10226290
申请日：2002-08-23
申请人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Hideo Aoki , Toshikazu Kumai , Kazuhiko Saito , Michio Nishimura , Michio Tanaka , Katsuo Yuhara , Shinya Nishio , Toshiyuki Kaeriyama , Songsu Cho
发明人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Hideo Aoki , Toshikazu Kumai , Kazuhiko Saito , Michio Nishimura , Michio Tanaka , Katsuo Yuhara , Shinya Nishio , Toshiyuki Kaeriyama , Songsu Cho
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.
摘要翻译：在一个实施例中，DRAM具有其上表面和侧表面被第一绝缘膜覆盖的多个字线，多个位线设置成与字线绝缘并横向于字线并被覆盖具有第二绝缘膜和多个存储单元，每个存储单元设置在一个字线和一个位线之间的交点处，并且包括电容器和存储单元选择晶体管，其中用于在半导体区域和电容器之间以及半导体之间连接的接触孔区域和位线形成为自对准，并且第二绝缘膜由电容率小于第一绝缘膜的介电常数的材料制成。

5. 发明授权

US06287912B1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06287912B1
公开(公告)日：2001-09-11
申请号：US09389457
申请日：1999-09-03
申请人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura
发明人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823857 , H01L27/10852 , H01L27/10873 , Y10S438/981
摘要： A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.
摘要翻译：通过图案化光致抗蚀剂膜形成用于蚀刻形成在栅极绝缘膜形成区域中的相对薄的栅极绝缘膜的掩模，并且该掩模用于引入用于调节n沟道场效应晶体管的阈值电压的杂质和p - 沟道场效应晶体管，其具有相对较薄的栅极绝缘膜到半导体衬底上未被掩模覆盖的区域。

6. 发明授权

US6060352A Method of manufacturing semiconductor device with increased focus margin 失效
标题翻译：具有增加焦距的半导体器件的制造方法
公开(公告)号：US6060352A
公开(公告)日：2000-05-09
申请号：US15073
申请日：1998-01-28
申请人： Toshihiro Sekiguchi , Hideo Aoki , Yoshitaka Tadaki , Keizo Kawakita , Jun Murata , Katsuo Yuhara , Michio Nishimura , Kazuhiko Saitoh , Minoru Ohtsuka , Masayuki Yasuda , Toshiyuki Kaeriyama , Songsu Cho
发明人： Toshihiro Sekiguchi , Hideo Aoki , Yoshitaka Tadaki , Keizo Kawakita , Jun Murata , Katsuo Yuhara , Michio Nishimura , Kazuhiko Saitoh , Minoru Ohtsuka , Masayuki Yasuda , Toshiyuki Kaeriyama , Songsu Cho
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for fabricating DRAMs each having a COB structure, and the semiconductor device formed by this method, are provided. In one embodiment, the word line and/or bit line is covered with an insulating film having a comparatively small etching rate. Contact holes are formed while being defined by those insulating films in self-alignment.
摘要翻译：提供了一种用于制造各自具有COB结构的DRAM的方法，以及通过该方法形成的半导体器件。在一个实施例中，字线和/或位线被具有相对较小蚀刻速率的绝缘膜覆盖。在由这些绝缘膜以自对准的方式限定的同时形成接触孔。

7. 发明授权

US5933724A Method of manufacturing a semiconductor integrated circuit device using a photomask in which transmitted light beam intensities are controlled 失效
标题翻译：使用其中控制透射光束强度的光掩模制造半导体集成电路器件的方法
公开(公告)号：US5933724A
公开(公告)日：1999-08-03
申请号：US703067
申请日：1996-08-26
申请人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Jun Murata , Katsuo Yuhara , Toshikazu Kumai , Michio Tanaka , Michio Nishimura , Kazuhiko Saitoh , Takatoshi Kakizaki , Takeshi Sakai , Toshiyuki Kaeriyama , Songsu Cho
发明人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Jun Murata , Katsuo Yuhara , Toshikazu Kumai , Michio Tanaka , Michio Nishimura , Kazuhiko Saitoh , Takatoshi Kakizaki , Takeshi Sakai , Toshiyuki Kaeriyama , Songsu Cho
IPC分类号： G03F1/28 , G03F1/30 , G03F1/36 , G03F1/68 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852
摘要： A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.
摘要翻译：使用相移掩模来制造包括导体图案的半导体集成电路器件，其中图案化导体条的线宽或图案化导体条之间的空间不是恒定的。对于对应于导体图案的掩模中的主要透明区域，提供辅助图案段以补偿由线宽或空间的变化引起的透射光的相位分布的变化。或者，调节导体条之间的空间以抑制透射光的相分布的变化。辅助图案片段是否应该具有相移功能是根据主透明区域的配置来确定的。

8. 发明授权

US5930624A Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring 失效
标题翻译：具有开关MISFET和包括布线的电容元件的半导体集成电路器件的制造方法
公开(公告)号：US5930624A
公开(公告)日：1999-07-27
申请号：US13605
申请日：1998-01-26
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。在第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成在高压下通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

9. 发明授权

US5264712A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法及其制造装置
公开(公告)号：US5264712A
公开(公告)日：1993-11-23
申请号：US881314
申请日：1992-05-07
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L21/8234 , H01L27/105 , H01L21/308 , H01L29/66
CPC分类号： H01L27/105 , H01L21/823425
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
摘要翻译：一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

10. 发明授权

US08294225B2 Ultrasonic transducer and manufacturing method 有权
标题翻译：超声波换能器及制造方法
公开(公告)号：US08294225B2
公开(公告)日：2012-10-23
申请号：US12407414
申请日：2009-03-19
申请人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
发明人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
IPC分类号： H01L21/00
CPC分类号： B06B1/0292 , Y10T29/49005
摘要： This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.
摘要翻译：本发明提供一种技术，即使通过将下部电极分割成成分元件而产生台阶，也能够降低上部电极的电阻增加，膜的损伤以及上部电极与下部电极之间的介电强度的降低。在包括多个下电极的超声波换能器中，覆盖下电极的绝缘膜，形成为与绝缘膜上的下电极重叠的多个中空部，填充中空部之间的间隙的绝缘膜，覆盖中空部的绝缘膜，绝缘膜，形成为与绝缘膜上的中空部分重叠的多个上电极和连接它们的多个互连，中空部分和绝缘膜的表面被平坦化到相同的高度。

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