专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120208334A1 METHODS OF FABRICATING A DUAL POLYSILICON GATE AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：制造双聚硅酮门的方法和使用其制造半导体器件的方法
公开(公告)号：US20120208334A1
公开(公告)日：2012-08-16
申请号：US13365462
申请日：2012-02-03
申请人： Kyong Bong ROUH , Yong Seok EUN
发明人： Kyong Bong ROUH , Yong Seok EUN
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L21/28114 , H01L21/823842 , H01L29/42376
摘要： Methods of forming a dual polysilicon gate are provided. The method includes forming a polysilicon layer doped with impurities of a first conductivity type on a substrate having a first region and a second region, forming a mask pattern that covers the polysilicon layer in the first region and leaves the polysilicon layer in the second region, injecting impurities of a second conductivity type into the polysilicon layer in the second region left exposed by the mask pattern. Removing the mask pattern, and patterning the polysilicon layer to form a first polysilicon pattern in the first region and a second polysilicon pattern in the second region. The second polysilicon pattern is formed to have protrusions that laterally protrude from sidewalls thereof. Subsequently, impurities of the second conductivity type are injected into the substrate in the second region and into the protrusions of the second polysilicon pattern.
摘要翻译：提供了形成双重多晶硅栅极的方法。该方法包括在具有第一区域和第二区域的衬底上形成掺杂有第一导电类型的杂质的多晶硅层，形成覆盖第一区域中的多晶硅层并在第二区域中离开多晶硅层的掩模图案，将第二导电类型的杂质注入到由掩模图案留下的第二区域中的多晶硅层中。去除掩模图案，以及图案化多晶硅层以在第一区域中形成第一多晶硅图案，在第二区域形成第二多晶硅图案。第二多晶硅图案被形成为具有从其侧壁横向突出的突起。随后，将第二导电类型的杂质注入到第二区域中的衬底中并注入到第二多晶硅图案的突起中。

2. 发明授权

US07723189B2 Method for manufacturing semiconductor device having recess gate 失效
标题翻译：具有凹槽的半导体器件的制造方法
公开(公告)号：US07723189B2
公开(公告)日：2010-05-25
申请号：US11618565
申请日：2006-12-29
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76224 , H01L29/66583
摘要： A method for manufacturing a semiconductor device having recess gates includes forming an etch stop film on a semiconductor substrate; forming an etch stop film pattern selectively exposing the semiconductor substrate by patterning the etch stop film; forming a semiconductor layer on the semiconductor substrate; forming a hard mask film pattern exposing regions, for forming trenches for recess gates, on the semiconductor substrate; removing the semiconductor layer using the hard mask film pattern as a mask until the etch stop film pattern is exposed; forming the trenches for recess gates by removing the etch stop film pattern from the semiconductor substrate; and forming gate stacks, each of which is formed in the corresponding one of the trenches for recess gates.
摘要翻译：一种用于制造具有凹槽的半导体器件的方法包括在半导体衬底上形成蚀刻停止膜; 通过图案化所述蚀刻停止膜形成选择性地暴露所述半导体衬底的蚀刻停止膜图案; 在半导体衬底上形成半导体层; 在半导体衬底上形成用于形成用于凹槽的沟槽的暴露区域的硬掩模膜图案; 使用硬掩模膜图案作为掩模去除半导体层，直到蚀刻停止膜图案被曝光; 通过从半导体衬底去除蚀刻停止膜图案来形成凹槽的沟槽; 以及形成栅极堆叠，每个栅极堆叠形成在用于凹槽的相应的一个沟槽中。

3. 发明申请

US20090256209A1 Gate Structure of Semiconductor Device 有权
标题翻译：半导体器件的栅极结构
公开(公告)号：US20090256209A1
公开(公告)日：2009-10-15
申请号：US12485649
申请日：2009-06-16
申请人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
发明人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
IPC分类号： H01L27/088
CPC分类号： H01L27/10876 , H01L21/2815 , H01L29/66636
摘要： A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film.
摘要翻译：一种半导体器件的栅极结构，包括具有场氧化物膜的硅衬底，通过在硅衬底上依次层叠第一栅极电介质膜，第一栅极导电膜和栅极硅化物膜而形成的多个栅极。形成在第一栅极导电膜的一侧的热氧化膜，形成在栅极之间的多个沟槽，形成在每个沟槽的内壁上的第二栅极氧化膜; 以及在所述第二栅极氧化膜的预定区域上形成间隔物形状的第二导电膜，以及在所述第一栅极导电膜，所述栅极硅化物膜和所述热氧化物膜的一侧。

4. 发明授权

US07563673B2 Method of forming gate structure of semiconductor device 失效
标题翻译：形成半导体器件栅极结构的方法
公开(公告)号：US07563673B2
公开(公告)日：2009-07-21
申请号：US11268846
申请日：2005-11-08
申请人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
发明人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L21/2815 , H01L29/66636
摘要： Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.
摘要翻译：本文公开了一种用于形成半导体器件的栅极结构的方法。该方法包括形成多个栅极，其包括依次层叠在具有场氧化膜的硅基板上的第一栅极电介质膜，第一栅极导电膜和栅极硅化物膜，在第一栅极的一侧形成热氧化膜将暴露在所述多个栅极之间的硅衬底蚀刻到预定深度以形成多个沟槽，在所述沟槽的内壁上形成第二栅极氧化膜，并且形成间隔物形状的第二栅极导电膜第二栅极氧化膜的预定区域，以及第一栅极导电膜，栅极硅化物膜和热氧化物膜的一侧。

5. 发明授权

US06949480B2 Method for depositing silicon nitride layer of semiconductor device 失效
公开(公告)号：US06949480B2
公开(公告)日：2005-09-27
申请号：US10889477
申请日：2004-07-12
申请人： Hyung Kyun Kim , Sung Hoon Jung , Yong Seok Eun
发明人： Hyung Kyun Kim , Sung Hoon Jung , Yong Seok Eun
IPC分类号： H01L21/205 , C23C16/34 , H01L21/302 , H01L21/318 , H01L21/44 , H01L21/461
CPC分类号： H01L21/02271 , C23C16/345 , H01L21/0217 , H01L21/3185
摘要： Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.

6. 发明授权

US09275904B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09275904B2
公开(公告)日：2016-03-01
申请号：US12614991
申请日：2009-11-09
申请人： Sung-Jin Whang , Moon-Sig Joo , Yong-Seok Eun , Kwon Hong , Bo-Min Seo , Kyoung-Eun Chang , Seung-Woo Shin
发明人： Sung-Jin Whang , Moon-Sig Joo , Yong-Seok Eun , Kwon Hong , Bo-Min Seo , Kyoung-Eun Chang , Seung-Woo Shin
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/108 , H01L27/115 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823443 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/31051 , H01L21/31111 , H01L21/32139 , H01L27/10873 , H01L27/11521 , H01L27/11568 , H01L29/42376 , H01L29/4933
摘要： A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成栅极图案，形成覆盖每个栅极图案的顶部和侧壁的导电层，在导电层上形成用于硅化工艺的金属层，以及硅化导电层和栅极图案使用金属层。

7. 发明授权

US08513103B2 Method for manufacturing vertical transistor having buried junction 有权
标题翻译：用于制造具有埋入结的垂直晶体管的方法
公开(公告)号：US08513103B2
公开(公告)日：2013-08-20
申请号：US13252504
申请日：2011-10-04
申请人： Eun Shil Park , Yong Seok Eun , Kyong Bong Rouh
发明人： Eun Shil Park , Yong Seok Eun , Kyong Bong Rouh
IPC分类号： H01L21/425
CPC分类号： H01L29/7827 , H01L21/2257 , H01L21/26513 , H01L21/26586 , H01L21/32134 , H01L21/32139 , H01L27/10876 , H01L27/10888 , H01L29/0847 , H01L29/167 , H01L29/456 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening.
摘要翻译：在半导体器件的垂直晶体管中形成掩埋结。壁体由半导体基板形成，壁体在第一侧表面的相对侧具有第一侧表面和第二侧表面而突出; 形成具有开口的一侧接触掩模，所述开口选择性地打开所述壁体的所述第一侧表面的一部分; 以及通过将具有不同扩散性的杂质扩散到暴露于所述开口的所述第一侧表面的部分中，形成围绕所述第一杂质层的第一杂质层和第二杂质层。

8. 发明授权

US08481390B2 Method for forming impurity region of vertical transistor and method for fabricating vertical transistor using the same 有权
标题翻译：用于形成垂直晶体管的杂质区域的方法及使用其制造垂直晶体管的方法
公开(公告)号：US08481390B2
公开(公告)日：2013-07-09
申请号：US13084220
申请日：2011-04-11
申请人： Yong Seok Eun , Tae Kyun Kim , Kyong Bong Rouh , Eun Shil Park
发明人： Yong Seok Eun , Tae Kyun Kim , Kyong Bong Rouh , Eun Shil Park
IPC分类号： H01L21/336
CPC分类号： H01L21/266 , H01L21/26513 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
摘要翻译：用于形成垂直晶体管的杂质区域的方法包括在半导体衬底内形成杂质离子结区域，并通过蚀刻形成杂质离子结区域的半导体衬底形成沟槽。执行蚀刻处理以去除杂质离子结区域的一部分，使得杂质离子接合区域的剩余部分暴露于沟槽的下侧壁以用作掩埋位线结区域。

9. 发明申请

US20130161767A1 SEMICONDUCTOR DEVICES HAVING POLYSILICON GATE PATTERNS AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：具有多晶硅栅格图案的半导体器件及其制造方法
公开(公告)号：US20130161767A1
公开(公告)日：2013-06-27
申请号：US13615312
申请日：2012-09-13
申请人： Kyong Bong ROUH , Yong Seok EUN , Young Jin SON
发明人： Kyong Bong ROUH , Yong Seok EUN , Young Jin SON
IPC分类号： H01L29/78 , H01L21/425
CPC分类号： H01L29/4941 , H01L21/28035 , H01L29/4925
摘要： A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.
摘要翻译：一种在衬底上包括栅极绝缘图案的半导体器件，以及堆叠在与衬底相对的栅极绝缘图案侧的非晶硅图案和多晶硅图案的半导体栅极图案。非晶硅图案包括抑制杂质离子在半导体栅极图案中的扩散的抗扩散杂质。

10. 发明申请

US20120208364A1 METHOD FOR OPENING ONE-SIDE CONTACT REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING ONE-SIDE JUNCTION REGION USING THE SAME 有权
标题翻译：用于打开垂直晶体管的单面接触区域的方法和使用该方法制造单面结区的方法
公开(公告)号：US20120208364A1
公开(公告)日：2012-08-16
申请号：US13161846
申请日：2011-06-16
申请人： Kyong Bong ROUH , Yong Seok EUN , Eun Shil PARK
发明人： Kyong Bong ROUH , Yong Seok EUN , Eun Shil PARK
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L21/32155 , H01L21/2236 , H01L21/2257 , H01L21/26586 , H01L21/31144 , H01L21/32134 , H01L27/10876 , H01L27/10888 , H01L29/66666 , H01L29/7827
摘要： A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.
摘要翻译：提供了一种用于打开垂直晶体管的单侧接触区域的方法。使用多晶硅层打开垂直晶体管的单面接触区域，通过选择性离子注入工艺可以选择性地去除其中的一部分。为了选择性地去除形成在要形成单面接触的有源区的两侧的多晶硅层，通过等离子体掺杂工艺在与多晶硅层垂直的方向上进行杂质离子注入，并且使用现有的离子注入工艺进行倾斜离子注入。以这种方式，选择性地掺杂多晶硅层，并且选择性地去除多晶硅层的未掺杂部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式