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1. 发明申请

US20070120611A1 Phase frequency detector capable of improving noise characteristics 失效
标题翻译：相位检波器能够改善噪声特性
公开(公告)号：US20070120611A1
公开(公告)日：2007-05-31
申请号：US11549046
申请日：2006-10-12
申请人： Yoo Hwan KIM , Ki Sung KWON , Soo Woong LEE , Jin Taek LEE , Yo Sub MOON , Sung Cheol SHIN , Gyu Suck KIM
发明人： Yoo Hwan KIM , Ki Sung KWON , Soo Woong LEE , Jin Taek LEE , Yo Sub MOON , Sung Cheol SHIN , Gyu Suck KIM
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03D13/003 , H03D13/004 , H03L7/085 , H03L7/18
摘要： A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.
摘要翻译：公开了一种用于改善PLL的带内相位噪声特性的相位频率检测器。相位频率检测器将参考频率与通过将压控振荡器（VCO）的输出频率除以预定分频比而产生的分频，将与基准频率和分频之间的相位差相对应的相位差信号进行比较频率，并改善噪声特性。

2. 发明授权

US07282969B2 Low divide ratio programmable frequency divider and method thereof 失效
标题翻译：低分频比可编程分频器及其方法
公开(公告)号：US07282969B2
公开(公告)日：2007-10-16
申请号：US11380917
申请日：2006-04-28
申请人： Sung Cheol Shin , Yoo Hwan Kim , Ki Sung Kwon , Soo Woong Lee , Jin Taek Lee , Yo Sub Moon
发明人： Sung Cheol Shin , Yoo Hwan Kim , Ki Sung Kwon , Soo Woong Lee , Jin Taek Lee , Yo Sub Moon
IPC分类号： H03K21/00
CPC分类号： H03K23/68 , H03L7/1978
摘要： The invention provides a low divide ratio programmable frequency divider of a fractional-N type applied to a digital MOPLL tuner and a method thereof. In the invention, a divide ratio assigner assigns divide data as a main divide ratio and a pulse swallow value according to a first or a second dividing operation mode in response to a mode selection signal. A prescaler operates on the first or second divide operation mode in response to the mode selection signal. Also, a main counter divides a frequency from the prescaler by the main divide ratio. Further, a pulse swallow counter counts a clock of the main counter while outputting a pulse swallow signal to the prescaler. The pulse swallow signal has a swallow level if a counting value corresponds to the pulse swallow value, and a non-swallow level if the counting value does not correspond to the pulse swallow value.
摘要翻译：本发明提供一种应用于数字MOPLL调谐器的分数N型的低分频比可编程分频器及其方法。在本发明中，分频比分配器响应于模式选择信号，根据第一或第二分频操作模式分配除数数据作为主分频比和脉冲吞咽值。预分频器响应于模式选择信号在第一或第二除法运算模式下操作。另外，主计数器将预分频器的频率除以主分频比。此外，脉冲吞咽计数器计数主计数器的时钟，同时向预分频器输出脉冲吞咽信号。如果计数值对应于脉冲吞咽值，则脉冲吞咽信号具有吞咽水平，如果计数值与脉冲吞咽值不对应，则为非吞咽水平。

3. 发明申请

US20120161750A1 ELECTRONIC WATT-HOUR METER AND METHOD OF CALCULATING WATT-HOURS 审中-公开
标题翻译：电子花式计时器和计算时间的方法
公开(公告)号：US20120161750A1
公开(公告)日：2012-06-28
申请号：US13038670
申请日：2011-03-02
申请人： Yo Sub MOON
发明人： Yo Sub MOON
IPC分类号： G01R21/06
CPC分类号： G01R21/133 , G01R22/10
摘要： Disclosed is an electronic watt-hour meter including: a plurality of sigma-delta modulators converting a plurality of analog detection currents, acquired by detecting currents flowing through a plurality of power lines having different phases, and a plurality of analog detection voltages, acquired by detecting voltages applied to the plurality of power lines, into respective bitstreams; a first register storing the bitstreams of the plurality of detection currents; a second register storing the bitstreams of the plurality of detection voltages; a register controller controlling the first register and the second register to sequentially output the bitstreams of the plurality of detection currents and the bitstreams of the plurality of detection voltages while simultaneously outputting bitstreams of detection currents and bitstreams of detection voltages detected in the same power line; a first decimation filter converting the bitstreams of the plurality of detection currents sequentially outputted from the first register into digital values; and a second decimation filter converting the bitstreams of the plurality of detection voltages sequentially outputted from the second register into digital values.
摘要翻译：公开了一种电子电度表，包括：多个Σ-Δ调制器，其转换通过检测流过具有不同相位的多个电力线的电流而获取的多个模拟检测电流，以及多个模拟检测电压，通过将施加到所述多条电力线的电压检测到各个比特流中; 存储多个检测电流的比特流的第一寄存器; 存储多个检测电压的比特流的第二寄存器; 控制所述第一寄存器和所述第二寄存器的寄存器控制器，以顺序地输出所述多个检测电流的比特流和所述多个检测电压的比特流，同时输出在同一电力线中检测的检测电流和检测电压的位流的比特流; 第一抽取滤波器，将从第一寄存器顺序输出的多个检测电流的比特流转换为数字值; 以及第二抽取滤波器，将从第二寄存器顺序输出的多个检测电压的比特流转换为数字值。

4. 发明申请

US20100073081A1 INTEGRATED TRACKING FILTER 审中-公开
标题翻译：集成跟踪过滤器
公开(公告)号：US20100073081A1
公开(公告)日：2010-03-25
申请号：US12394677
申请日：2009-02-27
申请人： Yo Sub MOON , Jeong Ki Choi , Yoo Hwan Kim , Gyu Suck Kim , Kyoung Seok Park
发明人： Yo Sub MOON , Jeong Ki Choi , Yoo Hwan Kim , Gyu Suck Kim , Kyoung Seok Park
IPC分类号： H03K5/00
CPC分类号： H03H11/1291
摘要： An integrated tracking filter includes: an amplifying unit having first to third terminals, the first terminal being connected to an input stage and the second terminal being connected to an output stage, and amplifying a signal from the input stage; a loading unit connected between a power source stage and the second terminal of the amplifying unit; a current source connected between the third terminal of the amplifying unit and a ground; and a switched LC filter unit connected between the third terminal of the amplifying unit and the ground and varying a pass band of the signal.
摘要翻译：集成跟踪滤波器包括：放大单元，具有第一至第三端子，第一端子连接到输入级，第二端子连接到输出级，并且放大来自输入级的信号; 连接在电源级与放大单元的第二端子之间的负载单元; 连接在放大单元的第三端子与地之间的电流源; 以及连接在放大单元的第三端子和地之间并改变信号的通带的开关LC滤波器单元。

5. 发明授权

US07463100B2 Phase frequency detector capable of improving noise characteristics 失效
标题翻译：相位检波器能够改善噪声特性
公开(公告)号：US07463100B2
公开(公告)日：2008-12-09
申请号：US11549046
申请日：2006-10-12
申请人： Yoo Hwan Kim , Ki Sung Kwon , Soo Woong Lee , Jin Taek Lee , Yo Sub Moon , Sung Cheol Shin , Gyu Suck Kim
发明人： Yoo Hwan Kim , Ki Sung Kwon , Soo Woong Lee , Jin Taek Lee , Yo Sub Moon , Sung Cheol Shin , Gyu Suck Kim
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03D13/003 , H03D13/004 , H03L7/085 , H03L7/18
摘要： A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.
摘要翻译：公开了一种用于改善PLL的带内相位噪声特性的相位频率检测器。相位频率检测器将参考频率与通过将压控振荡器（VCO）的输出频率除以预定分频比而产生的分频，将与基准频率和分频之间的相位差相对应的相位差信号进行比较频率，并改善噪声特性。

6. 发明申请

US20080180138A1 METHOD OF DETERMINING FRACTIONAL DIVIDE RATIO USING SIGMA-DELTA MODULATOR 审中-公开
标题翻译：使用SIGMA-DELTA调制器确定分数分辨率的方法
公开(公告)号：US20080180138A1
公开(公告)日：2008-07-31
申请号：US11533132
申请日：2006-09-19
申请人： Sung Cheol SHIN , Yoo Hwan KIM , Ki Sung KWON , Yo Sub MOON
发明人： Sung Cheol SHIN , Yoo Hwan KIM , Ki Sung KWON , Yo Sub MOON
IPC分类号： H03K21/00
CPC分类号： H03L7/1976
摘要： The invention relates to method of determining a fractional division ratio using a sigma-delta modulator. In this method, the fractional division ratio of the sigma-delta modulator is set as k/q, where k is an integer input value of the sigma-delta modulator, and q is a value preset to determine a predetermined frequency resolution. A spur generated from the voltage controller oscillator according to the variation of k is measured while the value k is varied. When the spur takes place at a certain value of k where a frequency is lower than a predetermined reference frequency, the fractional division ratio is reset as k/(q+1) or k/(q−1) for the certain value of k. The reset fractional division ratio is provided to the divider.
摘要翻译：本发明涉及使用Σ-Δ调制器确定分数分数比的方法。在该方法中，将Σ-Δ调制器的分数除数设定为k / q，其中k是Σ-Δ调制器的整数输入值，q是为了确定预定的频率分辨率而预设的值。测量根据k的变化从电压控制器振荡器产生的杂散，同时改变值k。当杂散发生在频率低于预定参考频率的k的某个值时，对于某个k值，分数比被复位为k /（q + 1）或k /（q-1）。复位分数除法提供给分频器。

7. 发明申请

US20090280762A1 HIGH-ORDER HARMONIC REJECTION MIXER USING CURRENT STEERING TECHNIQUE 审中-公开
标题翻译：使用电流转向技术的高阶谐波抑制混频器
公开(公告)号：US20090280762A1
公开(公告)日：2009-11-12
申请号：US12259619
申请日：2008-10-28
申请人： Kyoung Seok PARK , Nam Heung KIM , Jeong Ki CHOI , Yo Sub MOON , Gyu Suck KIM , Seung Won SEO , Yoo Hwan KIM
发明人： Kyoung Seok PARK , Nam Heung KIM , Jeong Ki CHOI , Yo Sub MOON , Gyu Suck KIM , Seung Won SEO , Yoo Hwan KIM
IPC分类号： H04B1/16
CPC分类号： H03D7/1441 , H03D7/1483 , H03D2200/0043 , H03D2200/0086
摘要： A mixer includes, an input current generation unit generating an input current; a first path circuit unit including n number of transistors having sources connected in common to an output node of the input current generation unit; and a second path circuit unit including n number of transistors having sources connected in common to the output node of the input current generation unit, and respectively corresponding to the n number of transistors included in the first path circuit unit. Local oscillator signals sequentially phase-shifted by 180°/n are individually input to gates of the n number of transistors included in the first path circuit unit, and local oscillator signals having opposite phases to the local oscillator signals input to the gates of the corresponding transistors included in the first path circuit unit are individually input to gates of the n number of transistors included in the second path circuit unit.
摘要翻译：混合器包括：输入电流产生单元，其产生输入电流; 包括n个晶体管的第一路径电路单元，其源极共同连接到输入电流产生单元的输出节点; 以及第二路径电路单元，其包括n个晶体管，其源极共同连接到输入电流产生单元的输出节点，并且分别对应于包括在第一路径电路单元中的n个晶体管。顺序相移180°/ n的本地振荡器信号被分别输入到包括在第一路径电路单元中的n个晶体管的栅极，并且与本地振荡器信号相反的本地振荡器信号输入到相应的门包括在第一路径电路单元中的晶体管被单独地输入到包括在第二路径电路单元中的n个晶体管的栅极。

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