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1. 发明授权

US08610493B2 Bias circuit and analog integrated circuit comprising the same 有权
标题翻译：偏置电路和包含该偏置电路的模拟集成电路
公开(公告)号：US08610493B2
公开(公告)日：2013-12-17
申请号：US13243955
申请日：2011-09-23
申请人： Yi-Gyeong Kim , Bong Chan Kim , Min-Hyung Cho , Jong-Kee Kwon
发明人： Yi-Gyeong Kim , Bong Chan Kim , Min-Hyung Cho , Jong-Kee Kwon
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45248 , H03F2203/45514 , H03F2203/45541 , H03F2203/45551
摘要： Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.
摘要翻译：公开了一种偏置电路，其包括被配置为使用参考电流和可变电流产生偏置电压的偏置电压产生部件; 参考电流源部，被配置为将所述参考电流提供给所述偏置电压产生部; 以及电流调节部，被配置为向所述偏置电压生成部提供所述可变电流，并且根据至少两个输入信号的电压电平来调整所述可变电流的量。偏置电路可以防止功耗的增加，同时提高转换速率。

2. 发明授权

US08542139B2 Current switch driving circuit and digital to analog converter 有权
标题翻译：电流开关驱动电路和数模转换器
公开(公告)号：US08542139B2
公开(公告)日：2013-09-24
申请号：US13310606
申请日：2011-12-02
申请人： Min-Hyung Cho , Yi-Gyeong Kim , Jong-Kee Kwon
发明人： Min-Hyung Cho , Yi-Gyeong Kim , Jong-Kee Kwon
IPC分类号： H03M1/00
CPC分类号： H03K17/04106 , H03M1/06 , H03M1/66
摘要： Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.
摘要翻译：提供了产生用于驱动电流开关的信号的电流开关驱动电路和使用该电流开关的数模转换器。电流开关驱动电路包括：第一PMOS晶体管，源极端子连接到电源端子，栅极端子接收输入信号，漏极端子输出驱动信号;漏极端子连接的NMOS晶体管到第一PMOS晶体管的漏极端子，并且栅极端子接收输入信号;第二PMOS晶体管，其源极端子连接到NMOS晶体管的源极端子，栅极端子连接到偏置电压端子，并且漏极端子连接到接地端子，并且使得允许第二PMOS晶体管恒定地处于导通状态的控制电流源。

3. 发明申请

US20130099868A1 SOUND DETECTING CIRCUIT AND AMPLIFIER CIRCUIT THEREOF 有权
标题翻译：声音检测电路和放大器电路
公开(公告)号：US20130099868A1
公开(公告)日：2013-04-25
申请号：US13531437
申请日：2012-06-22
申请人： Yi-Gyeong KIM , Min-Hyung CHO , Tae Moon ROH , Jong-Kee KWON , Woo Seok YANG , Jongdae KIM
发明人： Yi-Gyeong KIM , Min-Hyung CHO , Tae Moon ROH , Jong-Kee KWON , Woo Seok YANG , Jongdae KIM
IPC分类号： H03F3/04
CPC分类号： H03F3/08
摘要： Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.
摘要翻译：公开了一种声音检测电路，其包括：感测单元，被配置为响应于声音信号的声压级产生AC信号; 放大单元，被配置为放大AC信号; 以及偏置电压产生单元，被配置为产生要提供给所述放大单元的偏置电压。偏置电压产生单元包括被配置为提供功率电流的电流源; 以及电流电压转换电路，被配置为将功率电流转换成偏置电压并且减少由于功率电流引起的噪声。

4. 发明授权

US08164491B2 Coefficient multiplier and digital delta-sigma modulator using the same 有权
标题翻译：系数乘法器和使用其的数字delta-sigma调制器
公开(公告)号：US08164491B2
公开(公告)日：2012-04-24
申请号：US12783294
申请日：2010-05-19
申请人： Min Hyung Cho , Yi Gyeong Kim , Jong Kee Kwon
发明人： Min Hyung Cho , Yi Gyeong Kim , Jong Kee Kwon
IPC分类号： H03M7/32
CPC分类号： H03M7/3004 , H03M7/3033 , H03M7/304
摘要： Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.
摘要翻译：提供了使用其的系数乘法器和数字Δ-Σ调制器。系数乘法器使用系数平均技术将各自的相关乘法器的输出信号的平均值作为有效系数，而不使用具有复杂结构的加法器并占据较大的码片面积。因此，系数乘法器与典型有符号数（CSD）系数乘法器相比，具有简单的硬件结构和小的芯片面积，并且采用系数乘法器的数字Δ-Σ调制器结构简单，体积小。

5. 发明授权

US07821341B2 Gain control device and amplifier using the same 有权
标题翻译：增益控制装置和放大器使用相同
公开(公告)号：US07821341B2
公开(公告)日：2010-10-26
申请号：US12507701
申请日：2009-07-22
申请人： Yi Gyeong Kim , Min Hyung Cho , Jong Kee Kwon
发明人： Yi Gyeong Kim , Min Hyung Cho , Jong Kee Kwon
IPC分类号： H03G3/10
CPC分类号： H03F3/45475 , H03F2203/45528 , H03F2203/45591
摘要： Provided are a gain control device and an amplifier using the gain control device. The gain control device includes a first input resistance unit having a first variable resistor whose resistance is linearly variable and a first fixed resistor respectively receiving a first input signal and a second input signal having a sign different from the first input signal and outputting current through a first output terminal, and a second input resistance unit having a second fixed resistor and a second variable resistor whose resistance is linearly variable respectively receiving the first input signal and the second input signal and outputting current through a second output terminal.Since the gain control device can separately perform dB-linear gain control, it is easily combined with a circuit, such as a continuous-time sigma-delta modulator (SDM), a continuous-time filter, and a continuous-time analog-to-digital converter (ADC), and enables miniaturization and low power consumption.
摘要翻译：提供了增益控制装置和使用增益控制装置的放大器。所述增益控制装置包括具有电阻为线性变化的第一可变电阻器和分别接收第一输入信号的第一固定电阻器和具有与第一输入信号不同的符号的第二输入信号的第一输入电阻单元，第一输出端子和具有第二固定电阻器和第二可变电阻器的第二输入电阻单元，其电阻为线性变化，分别接收第一输入信号和第二输入信号，并通过第二输出端子输出电流。由于增益控制装置可以单独执行dB线性增益控制，所以可以容易地与诸如连续时间Σ-Δ调制器（SDM），连续时间滤波器以及连续时间模拟到数字转换器（ADC），并实现小型化和低功耗。

6. 发明授权

US07545301B2 Multi-bit delta-sigma modulator 有权
标题翻译：多位delta-Σ调制器
公开(公告)号：US07545301B2
公开(公告)日：2009-06-09
申请号：US11950481
申请日：2007-12-05
申请人： Yi Gyeong Kim , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim
发明人： Yi Gyeong Kim , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim
IPC分类号： H03M3/00
CPC分类号： H03M3/374 , H03M3/338 , H03M3/424 , H03M3/45 , H03M3/452 , H03M3/454
摘要： A delta-sigma modulator having a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; a delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter. More particularly, the delta-sigma modulator has low distortion characteristics suitable for multi-bit fast operation, wherein a feedback signal is delayed by one clock period through the delay circuit and the differential delay circuit.
摘要翻译：一种Δ-Σ调制器，具有用于积分输入信号的第一积分器; 用于将积分信号转换为数字信号的模拟 - 数字转换器; 延迟电路，用于延迟模数转换器的输出信号; 以及用于差分地延迟模数转换器的输出信号的差分延迟电路。更具体地，Δ-Σ调制器具有适合于多位快速操作的低失真特性，其中通过延迟电路和差分延迟电路将反馈信号延迟一个时钟周期。

7. 发明申请

US20090128230A1 BAND-GAP REFERENCE VOLTAGE GENERATOR FOR LOW-VOLTAGE OPERATION AND HIGH PRECISION 失效
标题翻译：用于低电压运行和高精度的带隙参考电压发生器
公开(公告)号：US20090128230A1
公开(公告)日：2009-05-21
申请号：US12195260
申请日：2008-08-20
申请人： Jeong Jin Roh , Hyung Dong Roh , Hyoung-Joong Kim , Yi Gyeong Kim , Jong Kee Kwon
发明人： Jeong Jin Roh , Hyung Dong Roh , Hyoung-Joong Kim , Yi Gyeong Kim , Jong Kee Kwon
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： Provided is a band-gap reference voltage generator for low-voltage operation and high precision. The band-gap reference voltage generator minimizes voltage drop by connecting resistors in parallel to bipolar transistors, and cancels temperature dependence by properly adjusting a resistor of an output stage, so that it can provide a stable reference voltage that is unaffected by a change in temperature in spite of a low power supply voltage. Further, the band-gap reference voltage generator minimizes variation of the reference voltage caused by offset noise by switching of input and output voltages at input and output stages of a feedback amplifier, so that it can provide a precise reference voltage.
摘要翻译：提供一种用于低电压操作和高精度的带隙参考电压发生器。带隙参考电压发生器通过将电阻并联连接到双极晶体管来最小化电压降，并通过适当调整输出级的电阻来消除温度依赖性，从而可以提供不受温度变化影响的稳定参考电压尽管电源电压低。此外，带隙参考电压发生器通过切换反馈放大器的输入和输出级的输入和输出电压来最小化由偏移噪声引起的参考电压的变化，使得其可以提供精确的参考电压。

8. 发明申请

US20090121909A1 DYNAMIC ELEMENT-MATCHING METHOD, MULTI-BIT DAC USING THE METHOD, AND DELTA-SIGMA MODULATOR AND DELTA-SIGMA DAC INCLUDING THE MULTI-BIT DAC 有权
标题翻译：使用该方法的动态元件匹配方法，多位DAC，以及包括多位DAC的DELTA-SIGMA调制器和DELTA-SIGMA DAC
公开(公告)号：US20090121909A1
公开(公告)日：2009-05-14
申请号：US12195232
申请日：2008-08-20
申请人： Yi Gyeong KIM , Min Hyung Cho , Chong Ki Kwon
发明人： Yi Gyeong KIM , Min Hyung Cho , Chong Ki Kwon
IPC分类号： H03M3/00 , H03M1/66 , H03M1/80
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464 , H03M3/502
摘要： Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.
摘要翻译：提供了动态元件匹配方法，多位数模转换器（DAC）和具有多位DAC的多位DAC和Δ-ΣDAC的Δ-Σ调制器。动态元件匹配方法涉及防止从Δ-Σ模数转换器（ADC）的delta-sigma调制器和用于在A-Sigma模数转换器（ADC）中使用的多位DAC的周期性信号分量（带内音调） Δ-ΣDAC。每次选择一个单位元素一次时，根据简单算法以新的顺序选择单位元素，因此单位元素不被周期性地使用。因此，可以防止由传统的数据加权平均（DWA）算法引起的带内音调。

9. 发明授权

US07388533B2 Multi-bit sigma-delta modulator and digital-to-analog converter with one digital-to-analog capacitor 有权
标题翻译：多位Σ-Δ调制器和具有一个数模转换器的数/模转换器
公开(公告)号：US07388533B2
公开(公告)日：2008-06-17
申请号：US11588455
申请日：2006-10-27
申请人： Yi Gyeong Kim , Chong Ki Kwon , Jong Dae Kim , Min Hyung Cho , Seung Chul Lee , Gyu Hyun Kim
发明人： Yi Gyeong Kim , Chong Ki Kwon , Jong Dae Kim , Min Hyung Cho , Seung Chul Lee , Gyu Hyun Kim
IPC分类号： H03M1/82 , H03M3/00
CPC分类号： H03M3/352 , H03M3/424 , H03M3/464
摘要： A digital-to-analog converter (DAC) for a sigma-delta modulator is provided. The DAC has a switched capacitor structure using an operational amplifier (OP amp) and performs a function exceeding 3-level using a switching method employing only one capacitor in single ended form. Thus, DAC non-linearity caused by capacitor mismatching does not occur, and the number of output levels of the DAC is increased. Also, the DAC capacitor may be applied to a general DAC to increase the ratio of DAC output levels to capacitors.
摘要翻译：提供了一种用于Σ-Δ调制器的数模转换器（DAC）。 DAC具有使用运算放大器（OP放大器）的开关电容器结构，并且使用仅采用单端形式的一个电容器的开关方法来执行超过3电平的功能。因此，不会发生由电容器失配引起的DAC非线性，并且DAC的输出电平的数量增加。此外，DAC电容器可以被施加到通用DAC以增加DAC输出电平与电容器的比率。

10. 发明申请

US20130148456A1 VOLTAGE REGULATOR WITH IMPROVED LOAD REGULATION AND VOLTAGE REGULATING METHOD 审中-公开
标题翻译：具有改进的负载调节和电压调节方法的电压调节器
公开(公告)号：US20130148456A1
公开(公告)日：2013-06-13
申请号：US13545877
申请日：2012-07-10
申请人： Min-Hyung CHO , Yi-Gyeong KIM , Tae Moon ROH , Woo Seok YANG , Jong-Kee KWON , Jongdae KIM
发明人： Min-Hyung CHO , Yi-Gyeong KIM , Tae Moon ROH , Woo Seok YANG , Jong-Kee KWON , Jongdae KIM
IPC分类号： G05F1/10 , G11C5/14
CPC分类号： G11C5/145 , H02M3/073 , H02M2001/0045
摘要： Provided is a voltage supply circuit using a charge pump. The voltage supply circuit enhances charge pump output voltage fluctuation characteristics depending on load variation of a charge pump voltage generator (load regulation characteristics) when receiving an operation power supply voltage of the charge pump through a regulator. The voltage supply circuit is configured to feed back fluctuation of a charge pump output voltage to a charge pump voltage regulator. The fluctuation of the charge pump output voltage is compensated through fluctuation of an output voltage of the charge pump to active enhance the load regulation characteristics.
摘要翻译：提供了使用电荷泵的电压供给电路。当通过调节器接收电荷泵的操作电源电压时，电压供应电路根据电荷泵电压发生器的负载变化（负载调节特性）来增强电荷泵输出电压波动特性。电压供给电路被配置为将电荷泵输出电压的波动反馈到电荷泵电压调节器。通过电荷泵的输出电压的波动补偿电荷泵输出电压的波动，从而有效提高负载调节特性。

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