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1. 发明授权

US08610493B2 Bias circuit and analog integrated circuit comprising the same 有权
标题翻译：偏置电路和包含该偏置电路的模拟集成电路
公开(公告)号：US08610493B2
公开(公告)日：2013-12-17
申请号：US13243955
申请日：2011-09-23
申请人： Yi-Gyeong Kim , Bong Chan Kim , Min-Hyung Cho , Jong-Kee Kwon
发明人： Yi-Gyeong Kim , Bong Chan Kim , Min-Hyung Cho , Jong-Kee Kwon
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45248 , H03F2203/45514 , H03F2203/45541 , H03F2203/45551
摘要： Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.
摘要翻译：公开了一种偏置电路，其包括被配置为使用参考电流和可变电流产生偏置电压的偏置电压产生部件; 参考电流源部，被配置为将所述参考电流提供给所述偏置电压产生部; 以及电流调节部，被配置为向所述偏置电压生成部提供所述可变电流，并且根据至少两个输入信号的电压电平来调整所述可变电流的量。偏置电路可以防止功耗的增加，同时提高转换速率。

2. 发明授权

US08542139B2 Current switch driving circuit and digital to analog converter 有权
标题翻译：电流开关驱动电路和数模转换器
公开(公告)号：US08542139B2
公开(公告)日：2013-09-24
申请号：US13310606
申请日：2011-12-02
申请人： Min-Hyung Cho , Yi-Gyeong Kim , Jong-Kee Kwon
发明人： Min-Hyung Cho , Yi-Gyeong Kim , Jong-Kee Kwon
IPC分类号： H03M1/00
CPC分类号： H03K17/04106 , H03M1/06 , H03M1/66
摘要： Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.
摘要翻译：提供了产生用于驱动电流开关的信号的电流开关驱动电路和使用该电流开关的数模转换器。电流开关驱动电路包括：第一PMOS晶体管，源极端子连接到电源端子，栅极端子接收输入信号，漏极端子输出驱动信号;漏极端子连接的NMOS晶体管到第一PMOS晶体管的漏极端子，并且栅极端子接收输入信号;第二PMOS晶体管，其源极端子连接到NMOS晶体管的源极端子，栅极端子连接到偏置电压端子，并且漏极端子连接到接地端子，并且使得允许第二PMOS晶体管恒定地处于导通状态的控制电流源。

3. 发明申请

US20130099868A1 SOUND DETECTING CIRCUIT AND AMPLIFIER CIRCUIT THEREOF 有权
标题翻译：声音检测电路和放大器电路
公开(公告)号：US20130099868A1
公开(公告)日：2013-04-25
申请号：US13531437
申请日：2012-06-22
申请人： Yi-Gyeong KIM , Min-Hyung CHO , Tae Moon ROH , Jong-Kee KWON , Woo Seok YANG , Jongdae KIM
发明人： Yi-Gyeong KIM , Min-Hyung CHO , Tae Moon ROH , Jong-Kee KWON , Woo Seok YANG , Jongdae KIM
IPC分类号： H03F3/04
CPC分类号： H03F3/08
摘要： Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.
摘要翻译：公开了一种声音检测电路，其包括：感测单元，被配置为响应于声音信号的声压级产生AC信号; 放大单元，被配置为放大AC信号; 以及偏置电压产生单元，被配置为产生要提供给所述放大单元的偏置电压。偏置电压产生单元包括被配置为提供功率电流的电流源; 以及电流电压转换电路，被配置为将功率电流转换成偏置电压并且减少由于功率电流引起的噪声。

4. 发明申请

US20130027094A1 TRIANGULAR WAVE GENERATOR AND METHOD GENERATING TRIANGULAR WAVE THEREOF 有权
标题翻译：三角波发生器及其三角波产生方法
公开(公告)号：US20130027094A1
公开(公告)日：2013-01-31
申请号：US13488337
申请日：2012-06-04
申请人： Hui Dong LEE , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
发明人： Hui Dong LEE , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
IPC分类号： H03K4/06
CPC分类号： H03K4/501
摘要： Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.
摘要翻译：公开了一种三角波发生器，其包括方波信号生成单元，其被配置为响应于时钟信号的第一转换，经由输出端子输出从低电平转换到高电平的第一信号，并且将第一信号转换为响应于复位信号从高电平的低电平; 电阻单元，被配置为调整所述方波信号的电压电平; 以及电容单元，被配置为接收电阻单元的输出信号，以产生从具有斜率的低电平上升到高电平的第二信号，以将复位信号提供给方波信号生成单元，并输出三角形通过从具有斜率的高电平将第二信号降低到低电平来产生信号。

5. 发明授权

US08362938B2 Analog digital converting device 有权
标题翻译：模拟数字转换装置
公开(公告)号：US08362938B2
公开(公告)日：2013-01-29
申请号：US12982531
申请日：2010-12-30
申请人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/365 , H03M1/468
摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.
摘要翻译：提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。模拟数字转换装置包括子ADC和逐次逼近ADC。子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。

6. 发明申请

US20120268052A1 MOTOR CONTROL DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：电机控制装置及其控制方法
公开(公告)号：US20120268052A1
公开(公告)日：2012-10-25
申请号：US13443823
申请日：2012-04-10
申请人： Jaewon NAM , Young Kyun Cho , Hui Dong Lee , Yil Suk Yang , Jong-Kee Kwon , Jongdae Kim
发明人： Jaewon NAM , Young Kyun Cho , Hui Dong Lee , Yil Suk Yang , Jong-Kee Kwon , Jongdae Kim
IPC分类号： H02P23/00
CPC分类号： H02P6/182 , H02P6/085 , H02P6/10 , H02P6/18 , H02P6/21 , H02P2209/07
摘要： A motor control device including a preprocessing portion calculating a counter electromotive force using an analog operation is provided. The motor control device may include an offset compensation portion and a counter electromotive force measuring portion. The offset compensation portion receives a three-phase current signal from the motor and compensates an offset of the three-phase current signal. The counter electromotive force measuring portion receives the compensated current signal and a three-phase voltage signal from the motor and calculates the received current signal and the received voltage signal using an analog operation to provide the calculated result.
摘要翻译：提供了一种包括使用模拟操作来计算反电动势的预处理部分的电动机控制装置。马达控制装置可以包括偏移补偿部分和反电动势测量部分。偏移补偿部分接收来自马达的三相电流信号，并补偿三相电流信号的偏移。反电动势测量部分接收来自电动机的补偿的电流信号和三相电压信号，并使用模拟操作来计算接收的电流信号和接收的电压信号，以提供计算结果。

7. 发明申请

US20120242266A1 SENSORLESS BLDC MOTOR SYSTEMS AND DRIVING METHODS OF SENSORLESS BLDC MOTOR 有权
标题翻译：无传感器BLDC电动机的传感器和驱动方法
公开(公告)号：US20120242266A1
公开(公告)日：2012-09-27
申请号：US13347128
申请日：2012-01-10
申请人： Young Kyun CHO , Hui Dong LEE , Jaewon NAM , Jong-Kee KWON
发明人： Young Kyun CHO , Hui Dong LEE , Jaewon NAM , Jong-Kee KWON
IPC分类号： H02P6/18
CPC分类号： H02P6/142 , H02P6/15
摘要： Provided is a sensorless BLDC motor system. The sensorless BLDC motor system includes a BLDC motor, a comparator, a motor controller, a three-phase inverter, and a mode selector. The BLDC motor includes first to third coils. The comparator compares a voltage of a specific coil of the first to third coils with a neutral-point voltage to output the compared result. The voltage of the specific coil becomes equal to the neutral-point voltage and a specific time elapses, and then the motor controller generates first and second coil control signals based on the compared result. The three-phase inverter supplies a source voltage or ground voltage to the specific coil, or floats the specific coil, in response to the first and second coil control signals. The mode selector selects a driving mode of the BLDC motor by adjusting the specific time.
摘要翻译：提供无传感器BLDC电机系统。无传感器BLDC电机系统包括BLDC电机，比较器，电机控制器，三相逆变器和模式选择器。 BLDC电机包括第一至第三线圈。比较器将第一至第三线圈的特定线圈的电压与中性点电压进行比较，以输出比较结果。特定线圈的电压等于中性点电压，经过一定时间，然后电机控制器根据比较结果产生第一和第二线圈控制信号。三相逆变器响应于第一和第二线圈控制信号向特定线圈提供源极电压或接地电压，或者浮动特定线圈。模式选择器通过调整具体时间来选择BLDC电机的驱动模式。

8. 发明授权

US08274317B2 Phase-locked loop circuit comprising voltage-controlled oscillator having variable gain 失效
标题翻译：锁相环电路包括具有可变增益的压控振荡器
公开(公告)号：US08274317B2
公开(公告)日：2012-09-25
申请号：US12882132
申请日：2010-09-14
申请人： Sang Hyun Cho , Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon , Seung Tak Ryu
发明人： Sang Hyun Cho , Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon , Seung Tak Ryu
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03L7/099 , H03L2207/06
摘要： A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.
摘要翻译：提供了包括具有可变增益的压控振荡器（VCO）的锁相环（PLL）电路。相位频率检测器（PFD）检测参考信号和PLL反馈信号之间的相位差。电荷泵和环路滤波器依次处理PFD的输出信号。根据模式转换，VCO具有不同的增益。根据模式转换，从环路滤波器的输出信号和附加控制信号中选择施加到VCO的控制电压。

9. 发明授权

US08164497B2 Pipeline analog-to-digital converter 有权
标题翻译：管道模数转换器
公开(公告)号：US08164497B2
公开(公告)日：2012-04-24
申请号：US12777910
申请日：2010-05-11
申请人： Jae Won Nam , Young Deuk Jeon , Young Kyun Cho , Jong Kee Kwon
发明人： Jae Won Nam , Young Deuk Jeon , Young Kyun Cho , Jong Kee Kwon
IPC分类号： H03M1/00
CPC分类号： H03M1/0836 , H03M1/168
摘要： Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.
摘要翻译：提供了一种没有前端采样和保持放大器（SHA）的流水线模数转换器（ADC）。为了最小化由于去除前端SHA而导致的闪存ADC和第一子范围ADC的乘法数模转换器（MDAC）之间的采样误差，包括在闪存ADC中的前置放大器的延迟时间并且闪速ADC比模拟输入信号稍后采样延迟时间比MDAC。因此，流水线ADC可以在不使用前端SHA的情况下最小化采样误差，并且可以减少其芯片面积和功耗。

10. 发明授权

US08164491B2 Coefficient multiplier and digital delta-sigma modulator using the same 有权
标题翻译：系数乘法器和使用其的数字delta-sigma调制器
公开(公告)号：US08164491B2
公开(公告)日：2012-04-24
申请号：US12783294
申请日：2010-05-19
申请人： Min Hyung Cho , Yi Gyeong Kim , Jong Kee Kwon
发明人： Min Hyung Cho , Yi Gyeong Kim , Jong Kee Kwon
IPC分类号： H03M7/32
CPC分类号： H03M7/3004 , H03M7/3033 , H03M7/304
摘要： Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.
摘要翻译：提供了使用其的系数乘法器和数字Δ-Σ调制器。系数乘法器使用系数平均技术将各自的相关乘法器的输出信号的平均值作为有效系数，而不使用具有复杂结构的加法器并占据较大的码片面积。因此，系数乘法器与典型有符号数（CSD）系数乘法器相比，具有简单的硬件结构和小的芯片面积，并且采用系数乘法器的数字Δ-Σ调制器结构简单，体积小。

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