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1. 发明授权

US08749260B2 Test wafer unit and test system 失效
标题翻译：测试晶圆单元和测试系统
公开(公告)号：US08749260B2
公开(公告)日：2014-06-10
申请号：US12947713
申请日：2010-11-16
申请人： Yasuo Tokunaga , Yoshio Komoto
发明人： Yasuo Tokunaga , Yoshio Komoto
IPC分类号： G01R31/00
CPC分类号： G01R31/318511 , G01R31/31723
摘要： Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.
摘要翻译：提供了一种测试晶片单元，其测试在被测晶片上形成的多个待测器件，该测试晶片单元包括形成在同一半导体晶片上的多个测试电路，其中多种类型的测试电路具有为每个待测设备提供不同的功能; 以及选择部，其选择哪种类型的测试电路电连接到被测器件的每个焊盘。因此，测试晶片单元可以选择与要执行的测试内容相对应的测试电路，并将该测试电路连接到被测器件，以对被测设备上的各种器件进行测试，或者对被测器件进行各种测试。

2. 发明授权

US08624620B2 Test system and write wafer 有权
标题翻译：测试系统和写晶圆
公开(公告)号：US08624620B2
公开(公告)日：2014-01-07
申请号：US12952110
申请日：2010-11-22
申请人： Yasuo Tokunaga , Yoshio Komoto
发明人： Yasuo Tokunaga , Yoshio Komoto
IPC分类号： G01R31/02
CPC分类号： G01R31/318511 , G01R31/2889 , G11C29/006 , G11C29/56 , G11C29/56016 , G11C2029/5602
摘要： A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.
摘要翻译：用于测试形成在半导体晶片上的多个半导体芯片的测试系统包括：测试晶片，其上形成有与多个半导体芯片对应的多个测试电路，每个测试电路测试多个半导体芯片中的相应一个半导体芯片基于提供给测试电路的测试数据; 其中多个测试电路中的每一个包括用于存储诸如模式数据和序列数据的测试数据的非易失性和可重写模式存储器，并且测试系统并行地向所有多个测试电路写入相同的测试数据。

3. 发明申请

US20110115519A1 TEST SYSTEM AND WRITE WAFER 有权
标题翻译：测试系统和写波形
公开(公告)号：US20110115519A1
公开(公告)日：2011-05-19
申请号：US12952110
申请日：2010-11-22
申请人： Yasuo TOKUNAGA , Yoshio KOMOTO
发明人： Yasuo TOKUNAGA , Yoshio KOMOTO
IPC分类号： G01R31/26
CPC分类号： G01R31/318511 , G01R31/2889 , G11C29/006 , G11C29/56 , G11C29/56016 , G11C2029/5602
摘要： A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.
摘要翻译：用于测试形成在半导体晶片上的多个半导体芯片的测试系统包括：测试晶片，其上形成有与多个半导体芯片对应的多个测试电路，每个测试电路测试多个半导体芯片中的相应一个半导体芯片基于提供给测试电路的测试数据; 其中多个测试电路中的每一个包括用于存储诸如模式数据和序列数据的测试数据的非易失性和可重写模式存储器，并且测试系统并行地向所有多个测试电路写入相同的测试数据。

4. 发明授权

US4243262A Rear window structure for automobile 失效
标题翻译：汽车后窗结构
公开(公告)号：US4243262A
公开(公告)日：1981-01-06
申请号：US959244
申请日：1978-11-09
申请人： Yasuo Tokunaga , Kiyoshige Yamada
发明人： Yasuo Tokunaga , Kiyoshige Yamada
IPC分类号： B60J1/18
CPC分类号： B60J1/1884
摘要： An automobile rear window structure for closing a rear window opening formed in an automobile body, the opening having front and rear edges and opposite sides. The window closing structure includes a pair of rear pillars extending along both sides of the rear window opening and having trough sections formed therein. Transparent material closing the rear opening includes a rear section and a pair of side sections positioned on opposite sides of the rear section. The side sections have transverse curvatures which are contiguous with a transverse curvature of the rear section. The rear section is formed separately from the side sections and is arranged to cover the rear window opening and has an upper end hinged to the body for swinging movement between closed and open positions. The side sections are secured to the vehicle body at transversely outside portions of the pillars, with edges of the sections extending over the pillars so that the rear section and side sections provide a contiguous contour when the rear section is closed. Seals are provided to ensure water tightness.
摘要翻译：一种用于关闭形成在汽车车体中的后窗开口的汽车后窗结构，所述开口具有前后边缘和相对的两侧。窗关闭结构包括沿着后窗开口的两侧延伸并且在其中形成有槽部的一对后柱。关闭后开口的透明材料包括后部和位于后部的相对侧上的一对侧部。侧部具有与后部的横向曲率邻接的横向曲率。后部与侧部分开形成并且被设置成覆盖后窗开口，并且具有铰链到主体的上端，用于在关闭位置和打开位置之间摆动。侧部在支柱的横向外部部分处固定到车体上，部分的边缘在支柱上延伸，使得当后部部分关闭时，后部部分和侧部分段提供连续的轮廓。提供密封以确保水密性。

5. 发明申请

US20110133768A1 TEST WAFER UNIT AND TEST SYSTEM 失效
标题翻译：测试波形单元和测试系统
公开(公告)号：US20110133768A1
公开(公告)日：2011-06-09
申请号：US12947713
申请日：2010-11-16
申请人： Yasuo TOKUNAGA , Yoshio KOMOTO
发明人： Yasuo TOKUNAGA , Yoshio KOMOTO
IPC分类号： G01R31/00
CPC分类号： G01R31/318511 , G01R31/31723
摘要： Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.
摘要翻译：提供了一种测试晶片单元，其测试在被测晶片上形成的多个待测器件，该测试晶片单元包括形成在同一半导体晶片上的多个测试电路，其中多种类型的测试电路具有为每个待测设备提供不同的功能; 以及选择部，其选择哪种类型的测试电路电连接到被测器件的每个焊盘。因此，测试晶片单元可以选择与要执行的测试内容相对应的测试电路，并将该测试电路连接到被测器件，以对被测设备上的各种器件进行测试，或者对被测器件进行各种测试。

6. 发明授权

US5214284A Method and arrangement for testing and repairing an integrated circuit 失效
标题翻译：用于测试和修复集成电路的方法和布置
公开(公告)号：US5214284A
公开(公告)日：1993-05-25
申请号：US744933
申请日：1991-08-14
申请人： Yasuo Tokunaga , Jurgen Frosien
发明人： Yasuo Tokunaga , Jurgen Frosien
IPC分类号： G01R31/26 , G01Q70/00 , G01R31/302 , H01L21/66 , H01L21/82 , H01L23/525
CPC分类号： H01L22/22 , G01R31/302 , H01L23/5258 , H01L2924/0002
摘要： The invention relates to an arrangement for testing and repairing an inteted circuit in which the ion beam used for the repair simultaneously forms the corpuscular beam used for the test operation and one single beam generator is provided in order to generate this beam. Testing and repairing in one arrangement, without it being necessary to transfer the integrated circuit to be examined, reduces the expenditure in terms of time and cost.
摘要翻译：本发明涉及一种用于测试和修复集成电路的装置，其中用于修复的离子束同时形成用于测试操作的红色光束，并且提供一个单个光束发生器以便产生该光束。测试和修理在一个安排中，没有必要转移被检查的集成电路，减少了时间和成本方面的支出。

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