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1. 发明专利

GB201801695D0 Polarising display 未知
公开(公告)号：GB201801695D0
公开(公告)日：2018-03-21
申请号：GB201801695
申请日：2018-02-01
申请人： LI KUN , CHU DAPING , YOENTEM ALI OEZGUER , YANG HAINING

2. 发明申请

WO2012170740A3 BIOMARKER OF ASBESTOS EXPOSURE AND MESOTHELIOMA 审中-公开
标题翻译： ASBESTOS暴露的生物标志物和MESOTHELIOMA
公开(公告)号：WO2012170740A3
公开(公告)日：2013-04-04
申请号：PCT/US2012041428
申请日：2012-06-07
申请人： UNIV HAWAII , UNIV NEW YORK , YANG HAINING , CARBONE MICHELE , PASS HARVEY I
发明人： YANG HAINING , CARBONE MICHELE , PASS HARVEY I
IPC分类号： G01N33/53 , G01N33/574
CPC分类号： G01N33/57423 , G01N33/57484 , G01N33/6875
摘要： Several embodiments provided herein relate to methods of diagnosing asbestos exposure or mesothelioma. Several embodiments also relate to methods of differentiating whether a tumor of the lung is lung cancer or mesothelioma.
摘要翻译：本文提供的几个实施例涉及诊断石棉暴露或间皮瘤的方法。几个实施方案还涉及区分肺癌是肺癌还是间皮瘤的方法。

3. 发明申请

WO2011063292A2 SEMICONDUCTOR DEVICE HAVING STRAIN MATERIAL 审中-公开
标题翻译：具有应变材料的半导体器件
公开(公告)号：WO2011063292A2
公开(公告)日：2011-05-26
申请号：PCT/US2010057514
申请日：2010-11-19
申请人： QUALCOMM INC , YANG HAINING
发明人： YANG HAINING
IPC分类号： H01L21/8246
CPC分类号： H01L27/088 , H01L21/02107 , H01L21/486 , H01L21/76224 , H01L21/823807 , H01L27/112 , H01L27/1122 , H01L29/78 , H01L29/7843 , H03K17/687
摘要： A semiconductor device having strain material is disclosed. In a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to the first cell. The second cell includes a second gate between a second drain and a second source. The semiconductor device further includes a shallow trench isolation area between the first source and the second source. A first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain.
摘要翻译：公开了一种具有应变材料的半导体器件。在特定实施例中，半导体器件包括第一单元，其包括在第一漏极和第一源极之间的第一栅极。半导体器件还包括与第一单元相邻的第二单元。第二单元包括在第二漏极和第二源极之间的第二栅极。半导体器件还包括在第一源极和第二源极之间的浅沟槽隔离区域。在第一源极和第二源极上的第一量的应变材料大于在第一漏极和第二漏极上方的第二量的应变材料。

4. 发明申请

WO2010079005A1 METHOD FOR REDUCING TIP-TO-TIP SPACING BETWEEN LINES 审中-公开
标题翻译：用于减少线之间的提前间距的方法
公开(公告)号：WO2010079005A1
公开(公告)日：2010-07-15
申请号：PCT/EP2009/065847
申请日：2009-11-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , LI, Wai-Kin , YANG, Haining , COLBURN, Matthew
发明人： LI, Wai-Kin , YANG, Haining , COLBURN, Matthew
IPC分类号： G03F7/40 , G03F7/00 , B81C1/00
CPC分类号： G03F7/40 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： This invention provides a method for reducing tip-to-tip spacing between lines using a combination of photolithographic and copolymer self-assembling lithographic techniques. A mask layer is first formed over a substrate with a line structure. A trench opening of a width d is created in the mask layer. A layer of a self-assembling block copolymer is then applied over the mask layer. The block copolymer layer is annealed to form a single unit polymer block of a width or a diameter w which is smaller than d inside the trench opening. The single unit polymer block is selectively removed to form a single opening of a width or a diameter w inside the trench opening. An etch transfer process is performed using the single opening as a mask to form an opening in the line structure in the substrate.
摘要翻译：本发明提供了使用光刻和共聚物自组装光刻技术的组合来减少线之间的尖端到尖端间隔的方法。首先在具有线结构的衬底上形成掩模层。在掩模层中形成宽度为d的沟槽开口。然后将一层自组装嵌段共聚物施加在掩模层上。对嵌段共聚物层进行退火以在沟槽开口内形成宽度或直径w小于d的单一单元聚合物嵌段。选择性地去除单个单元聚合物嵌段以在沟槽开口内形成宽度或直径w的单个开口。使用单个开口作为掩模进行蚀刻转印处理，以在基板中的线结构中形成开口。

5. 发明申请

WO2008051674A3 ELECTRICAL FUSE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：电保险丝及其制造方法
公开(公告)号：WO2008051674A3
公开(公告)日：2008-08-28
申请号：PCT/US2007079375
申请日：2007-09-25
申请人： IBM , YANG CHIH-CHAO , YANG HAINING
发明人： YANG CHIH-CHAO , YANG HAINING
IPC分类号： G11C17/14
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a trench feature in a substrate, depositing fuse material in the trench feature and compressive stress liner material over the fuse material, and patterning the compressive stress liner material.
摘要翻译：半导体熔丝包括熔丝元件和减小熔丝元件的电迁移电阻的压应力衬垫。该方法包括在衬底中形成沟槽特征，在沟槽特征中沉积熔丝材料并将压应力衬垫材料沉积在熔丝材料上，以及对压应力衬垫材料进行图案化。

6. 发明申请

WO2008091558A1 HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT 审中-公开
标题翻译：混合互连结构，用于性能改进和可靠性增强
公开(公告)号：WO2008091558A1
公开(公告)日：2008-07-31
申请号：PCT/US2008/000740
申请日：2008-01-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-Chao , SHAW, Thomas, M. , WONG, Keith, Kwong, Hon , YANG, Haining, S.
发明人： YANG, Chih-Chao , SHAW, Thomas, M. , WONG, Keith, Kwong, Hon , YANG, Haining, S.
IPC分类号： H01L23/48
CPC分类号： H01L21/76841 , H01L21/7682 , H01L21/76831 , H01L23/481 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
摘要翻译：本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地，气隙。与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

7. 发明申请

WO2007127770A2 IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：改进的具有双栅导体的CMOS二极管及其形成方法
公开(公告)号：WO2007127770A2
公开(公告)日：2007-11-08
申请号：PCT/US2007/067361
申请日：2007-04-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ONSONGO, David, M. , RAUSCH, Werner , YANG, Haining, S.
发明人： ONSONGO, David, M. , RAUSCH, Werner , YANG, Haining, S.
IPC分类号： H01L23/62
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
摘要翻译：本发明提供了具有双栅极导体的改进的CMOS二极管结构。具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度导体。

8. 发明申请

WO2007024984A2 HIGH PERFORMANCE MOSFET COMPRISING A STRESSED GATE METAL SILICIDE LAYER AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：包含耐压门金属硅化物层的高性能MOSFET及其制造方法
公开(公告)号：WO2007024984A2
公开(公告)日：2007-03-01
申请号：PCT/US2006/032974
申请日：2006-08-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Haining, S.
发明人： YANG, Haining, S.
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823835 , H01L29/4933 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7845 , H01L29/7848
摘要： The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET.
摘要翻译：本发明涉及一种半导体器件，其包括至少一个包含源极区域，漏极区域，沟道区域，栅极介电层，栅极电极和一个或多个栅极侧壁间隔物的场效应晶体管（FET）。这种FET的栅电极包含本征应力的栅极金属硅化物层，其被一个或多个栅极侧壁间隔物侧向限制，并且被布置和构造用于在FET的沟道区域中产生应力。优选地，半导体器件包括至少一个p沟道FET，并且更优选地，p沟道FET具有栅极电极，其具有被一个或多个栅极侧壁间隔物侧向限制的本征应力栅极金属硅化物层，构造用于在FET的p沟道中产生压应力。

9. 发明申请

WO2005027192A3 STRUCTURE AND METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS 审中-公开
标题翻译：具有狭缝分离的外延延伸和源和漏区的应变通道CMOS晶体管的结构和方法
公开(公告)号：WO2005027192A3
公开(公告)日：2006-12-21
申请号：PCT/US2004028163
申请日：2004-08-30
申请人： IBM , DOKUMACI OMER , CHEN HUAJIE , CHIDAMBARRAO DURESETI , YANG HAINING S
发明人： DOKUMACI OMER , CHEN HUAJIE , CHIDAMBARRAO DURESETI , YANG HAINING S
IPC分类号： H01L29/73 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7848
摘要： A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.
摘要翻译：提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。应力由第一半导体晶格失配的第二半导体层施加。第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

10. 发明申请

WO2004088726A3 ISOTROPIC ETCH PROCESS FOR TOP PLATE PULL-BACK IN A METAL- INSULATOR- METAL CAPACITOR 审中-公开
标题翻译：金属绝缘子金属电容器中顶板回拉的等压蚀刻工艺
公开(公告)号：WO2004088726A3
公开(公告)日：2004-11-25
申请号：PCT/EP2004003540
申请日：2004-04-02
申请人： INFINEON TECHNOLOGIES AG , IBM , FAYAZ FAZIL MOHAMMED , KERST UWE , MEZZAPELLE JOSEPH , YANG HAINING
发明人： FAYAZ FAZIL MOHAMMED , KERST UWE , MEZZAPELLE JOSEPH , YANG HAINING
IPC分类号： H01L21/02 , H01L27/08 , H01L29/92
CPC分类号： H01L28/40 , H01L27/0805
摘要： A MIM capacitor includes a bottom plate (212), a capacitor dielectric (214) disposed over the bottom plate, and a top plate (216) disposed over the capacitor dielectric. An etch stop material (218) is disposed over the top plate, and the top plate has a width that is less than the width of the etch stop material width. The top plate edges may be pulled back during the removal of the resist (220) used to pattern the top plate, by the addition of chemistries in the resist etch that are adapted to pull-back or undercut the top plate edges (224) beneath the etch stop material.
摘要翻译： MIM电容器包括底板（212），设置在底板上的电容器电介质（214）和设置在电容器电介质上的顶板（216）。蚀刻停止材料（218）设置在顶板上方，并且顶板的宽度小于蚀刻停止材料宽度的宽度。在去除用于图案化顶板的抗蚀剂（220）期间，顶板边缘可以被拉回，通过在抗蚀剂蚀刻中添加适于将下面的顶板边缘（224）拉回或倒下的化学物质蚀刻停止材料。

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