专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007127770A2 IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：改进的具有双栅导体的CMOS二极管及其形成方法
公开(公告)号：WO2007127770A2
公开(公告)日：2007-11-08
申请号：PCT/US2007/067361
申请日：2007-04-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ONSONGO, David, M. , RAUSCH, Werner , YANG, Haining, S.
发明人： ONSONGO, David, M. , RAUSCH, Werner , YANG, Haining, S.
IPC分类号： H01L23/62
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
摘要翻译：本发明提供了具有双栅极导体的改进的CMOS二极管结构。具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度导体。

2. 发明申请

WO2018192626A1 MONTAGEKELLE FÜR DEN EINBAU VON FENSTERBÄNKEN UND VERFAHREN ZUR MONTAGE EINER FENSTERBANK MIT DIESER MONTAGEKELLE 审中-公开
公开(公告)号：WO2018192626A1
公开(公告)日：2018-10-25
申请号：PCT/DE2018/100361
申请日：2018-04-17
申请人： RAUSCH, Werner
发明人： RAUSCH, Werner
IPC分类号： E06B1/70 , B25B5/06
摘要： Die Erfindung betrifft eine Fensterbankmontagekelle für den Einbau von Fensterbänken (15) unter einem Fensterrahmen (11), bestehend aus einem Abstandselement (1), wobei das Abstandselement (1) eine obere Seite geeignet zur Anlage an eine untere Seite des Fensterrahmens (11) aufweist, einem Griffelement (2) und einem Klemmelement (4), wobei das Klemmelement (4) mit dem Griffelement (2) verbunden ist, und wobei das Abstandselement (1) mit einer Aussparung (11) versehen ist, wodurch es unterschiedlich hohe seitliche Seiten für die Montage unterschiedlich starker Fensterbänke (15) hat, und auf dem Klemmelement (4) angebracht ist, und wobei das Klemmelement (4) leicht überstehend in Bezug auf das Abstandselement (1) angeordnet ist. Die erfindungsgemäße Fensterbankmontagekelle ermöglicht in Verbindung mit einem Montagewinkel (6), der zwischen Klemmelement (4) und Abstandselement (1) steckbar ist, eine Montage einer Fensterbank (15) ohne Unterlegklötzchen und mit enormer Zeitersparnis. Die Erfindung betrifft ferner das hierzu korrespondierende Verfahren.

3. 发明公开

EP1290719A2 HALO-FREE NON-RECTIFYING CONTACT ON CHIP WITH HALO SOURCE/DRAIN DIFFUSION 有权
标题翻译：环状植入免费，不等于教学联系与HALO扩散区的芯片
公开(公告)号：EP1290719A2
公开(公告)日：2003-03-12
申请号：EP01931903.7
申请日：2001-05-23
申请人： International Business Machines Corporation , IBM United Kingdom Limited
发明人： CULP, James , NAYAK, Jawahar , RAUSCH, Werner , SHERONY, Melanie , VOLDMAN, Steven , ZAMDMER, Noah
IPC分类号： H01L21/00
CPC分类号： H01L29/4966 , H01L29/1083 , H01L29/7835
摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

4. 发明授权

EP1290719B1 HALO-FREE NON-RECTIFYING CONTACT ON CHIP WITH HALO DIFFUSION 有权
标题翻译：环状植入免费，不等于教学联系与HALO扩散区的芯片
公开(公告)号：EP1290719B1
公开(公告)日：2009-03-11
申请号：EP01931903.7
申请日：2001-05-23
申请人： International Business Machines Corporation
发明人： CULP, James IBM UK Ltd. Intell. Prop. Law , NAYAK, Jawahar , RAUSCH, Werner , SHERONY, Melanie c/o IBM UK Ltd. Intell. Prop. Law , VOLDMAN, Steven , ZAMDMER, Noah c/o IBM UK Ltd. Intell. Prop. Law.
IPC分类号： H01L21/00 , H01L29/10 , H01L29/49 , H01L29/78 , H01L29/739 , H01L29/861
CPC分类号： H01L29/4966 , H01L29/1083 , H01L29/7835
摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

5. 发明授权

EP2020029B1 IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 有权
标题翻译：与双门和梯子过程改进的CMOS二极管用于生产
公开(公告)号：EP2020029B1
公开(公告)日：2012-08-29
申请号：EP07761243.0
申请日：2007-04-25
申请人： International Business Machines Corporation
发明人： ONSONGO, David, M. c/o IBM United Kingdom Limited , RAUSCH, Werner , YANG, Haining, S.
IPC分类号： H01L29/66 , H01L29/739 , H01L29/78 , H01L23/62
CPC分类号： H01L29/7391 , H01L29/66356

6. 发明公开

EP2020029A2 IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 有权
标题翻译：与双门和梯子过程改进的CMOS二极管用于生产
公开(公告)号：EP2020029A2
公开(公告)日：2009-02-04
申请号：EP07761243.0
申请日：2007-04-25
申请人： International Business Machines Corporation
发明人： ONSONGO, David, M. , RAUSCH, Werner , YANG, Haining, S.
IPC分类号： H01L23/62
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式