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1. 发明授权

US08701054B2 Boosting transistor performance with non-rectangular channels 有权
标题翻译：用非矩形通道提高晶体管的性能
公开(公告)号：US08701054B2
公开(公告)日：2014-04-15
申请号：US13237818
申请日：2011-09-20
申请人： Victor Moroz , Munkang Choi , Xi-Wei Lin
发明人： Victor Moroz , Munkang Choi , Xi-Wei Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L21/266 , H01L27/0207 , H01L29/1033 , H01L29/41758
摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.
摘要翻译：粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

2. 发明申请

US20110309453A1 ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH ISOLATION ON TRANSISTOR PERFORMANCE 有权
标题翻译：晶体管通道的增加可以减少晶体管性能上的微分离分离的影响
公开(公告)号：US20110309453A1
公开(公告)日：2011-12-22
申请号：US13221747
申请日：2011-08-30
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
摘要翻译：粗略描述，晶体管沟道区域在某些相邻STI区域的水平上升高。优选地，与扩散区横向相邻的STI区域被抑制，与N沟道扩散区域纵向相邻的STI区也是如此。优选地，与P沟道扩散纵向相邻的STI区域不被抑制; 优选地，它们具有至少与扩散区域相同的高度。

3. 发明授权

US07681164B2 Method and apparatus for placing an integrated circuit device within an integrated circuit layout 有权
标题翻译：将集成电路器件放置在集成电路布局内的方法和装置
公开(公告)号：US07681164B2
公开(公告)日：2010-03-16
申请号：US11848524
申请日：2007-08-31
申请人： Xi-Wei Lin , Victor Moroz
发明人： Xi-Wei Lin , Victor Moroz
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation devices within the continuous row of diffusion so that the IC device can be electrically isolated from other IC devices. The system then biases the one or more isolation device so that the IC device is electrically isolated from other IC devices within the continuous row of diffusion.
摘要翻译：提出了一种将集成电路（IC）器件放置在IC芯片布局内的系统。在操作期间，系统接收要放置在IC芯片布局内的IC器件，其中IC芯片布局包括一个或多个连续的扩散行。接下来，系统将IC器件放置在连续的扩散行内。然后，系统确定IC器件是否与其他IC器件电隔离。如果是这样，系统将一个或多个隔离装置插入连续的扩散行内，使得IC器件可以与其它IC器件电隔离。然后，该系统偏置一个或多个隔离装置，使得IC器件与连续的扩散排中的其它IC器件电隔离。

4. 发明申请

US20090319960A1 Minimizing Effects of Interconnect Variations in Integrated Circuit Designs 有权
标题翻译：互连变化对集成电路设计的影响最小化
公开(公告)号：US20090319960A1
公开(公告)日：2009-12-24
申请号：US12505357
申请日：2009-07-17
申请人： Xi-Wei Lin
发明人： Xi-Wei Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068 , G06F2217/10
摘要： Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the adjusted value for the adjustment variable. In an embodiment, the adjustment is made in dependence upon a pre-calculated “interconnect optimization database” indicating combinations of values for the plurality of variables which have been pre-determined to minimize exposure of interconnect propagation delay to process variations affecting the subject variable. Different databases, or different entries in the same database, can be provided for minimizing exposure of interconnect propagation delay to process variations affecting each subject variable of interest.
摘要翻译：粗略地描述了用于布置集成电路的方法和装置，其中对象互连对于影响对象互连的传播延迟的多个变量具有预定值。调整一个变量的值被调整以最小化互连的传播延迟的暴露，从而导致主题制造变量的值的变化导致处理变化的变化，并且根据调节的调整值来开发修改的布局变量。在一个实施例中，根据预先计算的“互连优化数据库”进行调整，所述“互连优化数据库”指示已经预先确定的多个变量的值的组合，以使互连传播延迟的曝光最小化以影响影响主题变量的处理变化。可以提供不同的数据库或相同数据库中的不同条目，用于最小化互连传播延迟对影响感兴趣的每个受试者变量的处理变化的暴露。

5. 发明授权

US07542891B2 Method of correlating silicon stress to device instance parameters for circuit simulation 有权
标题翻译：将硅应力与电路仿真器件实例参数相关联的方法
公开(公告)号：US07542891B2
公开(公告)日：2009-06-02
申请号：US11470978
申请日：2006-09-07
申请人： Xi-Wei Lin , Victor Moroz , Dipankar Pramanik
发明人： Xi-Wei Lin , Victor Moroz , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.
摘要翻译：粗略描述，可以通过替代不同的应力分析器来更好地模拟晶体管的应力调整特性来修改标准SPICE模型。第一，标准，应力敏感的晶体管模型用于开发第一晶体管性能测量与可用作第二，不应力敏感晶体管模型的输入的一个或多个实例参数之间的数学关系。第二晶体管模型可以例如与第一模型相同，其应力灵敏度被禁用。此后，可以使用替代应力分析器来确定用于第一性能测量的应力调整值，并且可以使用数学关系将该值转换为一个或多个实例参数的特定值。然后将这些值提供给第二晶体管模型，以用于在电路仿真期间模拟特定晶体管的特性。

6. 发明申请

US20070202662A1 Managing integrated circuit stress using dummy diffusion regions 有权
标题翻译：使用虚拟扩散区管理集成电路应力
公开(公告)号：US20070202662A1
公开(公告)日：2007-08-30
申请号：US11364390
申请日：2006-02-27
申请人： Xi-Wei Lin , Dipankar Pramanik , Victor Moroz
发明人： Xi-Wei Lin , Dipankar Pramanik , Victor Moroz
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823814 , H01L29/7846
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

7. 发明授权

US06316834B1 Tungsten plugs for integrated circuits and method for making same 失效
标题翻译：用于集成电路的钨插头及其制造方法
公开(公告)号：US06316834B1
公开(公告)日：2001-11-13
申请号：US09392343
申请日：1999-09-08
申请人： Calvin T. Gabriel , Dipankar Pramanik , Xi-Wei Lin
发明人： Calvin T. Gabriel , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.
摘要翻译：根据本发明的使用钨丝塞的集成电路胶层的制造方法包括：（A）提供具有表面，中心，边缘和与该表面垂直的方向的基板; 和（B）在衬底的表面上溅射沉积胶层，使得在垂直于衬底边缘表面的方向上测量的胶层的边缘厚度为胶的中心厚度的至少105％层在垂直于衬底中心表面的方向上测量。在一些实施例中，在垂直于衬底边缘处的表面的方向上测量的所述胶层的边缘厚度在胶层的中心厚度的约105％至150％的范围内，其测量方向为垂直于在基板的中心处的表面，例如在垂直于基板中心的表面的方向上测量的胶层的中心厚度的约110％至120％的范围内。

8. 发明授权

US6143613A Selective exclusion of silicide formation to make polysilicon resistors 失效
标题翻译：选择性排除硅化物形成以制造多晶硅电阻
公开(公告)号：US6143613A
公开(公告)日：2000-11-07
申请号：US885378
申请日：1997-06-30
申请人： Xi-Wei Lin
发明人： Xi-Wei Lin
IPC分类号： H01L21/02 , H01L21/28 , H01L21/336 , H01L27/06
CPC分类号： H01L28/20 , H01L21/28052 , H01L27/0629 , H01L29/66507 , H01L29/6659 , H01L29/66545
摘要： A technique for processing an integrated circuit is disclosed. This technique includes the formation of a polysilicon resistor without silicide next to a polysilicon transistor gate with silicide. Prior to silicidation, an oxide layer coats both polysilicon structures. A portion of the oxide layer is removed by chemical-mechanical polishing to define a generally planar surface from the remaining oxide layer and reexposed portions of each polysilicon structure. A metal layer is deposited on the surface. The portion of the metal layer over the polysilicon resistor structure is removed through a lithographic procedure. A self-aligned silicidation procedure is performed to form a silicide from the metal remaining over the polysilicon gate structure. The formation of both structures is then completed.
摘要翻译：公开了一种用于处理集成电路的技术。该技术包括在硅化物旁边形成具有硅化物的多晶硅电阻器，而不用多晶硅晶体管栅极。在硅化之前，氧化物层涂覆多晶硅结构。通过化学机械抛光去除氧化物层的一部分，以从剩余的氧化物层和每个多晶硅结构的再曝光部分界定大致平坦的表面。金属层沉积在表面上。多晶硅电阻结构上的金属层的部分通过光刻过程被去除。执行自对准硅化程序以从保留在多晶硅栅极结构上的金属形成硅化物。然后完成两个结构的形成。

9. 发明授权

US5933739A Self-aligned silicidation structure and method of formation thereof 失效
标题翻译：自对准硅化物结构及其形成方法
公开(公告)号：US5933739A
公开(公告)日：1999-08-03
申请号：US927479
申请日：1997-09-11
申请人： Xi-Wei Lin
发明人： Xi-Wei Lin
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823443
摘要： The invention relates to integrated circuits and to methods of forming self-aligned silicidation structures. In an exemplary embodiment, a first insulating layer is formed on the surface of a semiconductor substrate which includes an electrode. A second insulating layer is formed over the first insulating layer and a photoresist pattern is formed over a silicide exclusion area. Exposed portions of the first and second insulating layers are removed by one or more etching steps, wherein an etchant used to remove the exposed portions of the second insulating layer has a higher selectivity for the second insulating layer than for the first insulating layer. A silicide layer can then be formed over the surface of the semiconductor substrate except for silicide exclusion areas. Modification of the profiles of features underlying the first insulating layer, such as sidewall spacer and field oxides can thereby be prevented.
摘要翻译：本发明涉及集成电路和形成自对准硅化物结构的方法。在示例性实施例中，在包括电极的半导体衬底的表面上形成第一绝缘层。在第一绝缘层上形成第二绝缘层，并且在硅化物排除区域上形成光致抗蚀剂图案。通过一个或多个蚀刻步骤去除第一和第二绝缘层的暴露部分，其中用于去除第二绝缘层的暴露部分的蚀刻剂对于第二绝缘层具有比对于第一绝缘层更高的选择性。然后可以在除了硅化物排除区域之外的半导体衬底的表面上形成硅化物层。因此可以防止第一绝缘层下面的特征的轮廓的修改，例如侧壁间隔物和场氧化物。

10. 发明授权

US5882998A Low power programmable fuse structures and methods for making the same 失效
标题翻译：低功率可编程熔丝结构及其制造方法
公开(公告)号：US5882998A
公开(公告)日：1999-03-16
申请号：US55018
申请日：1998-04-03
申请人： Harlan Lee Sur, Jr. , Subhas Bothra , Xi-Wei Lin , Martin H. Manley , Robert Payne
发明人： Harlan Lee Sur, Jr. , Subhas Bothra , Xi-Wei Lin , Martin H. Manley , Robert Payne
IPC分类号： H01C13/00 , H01L21/822 , H01L23/525 , H01L27/04 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011
摘要： Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.
摘要翻译：公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。熔丝结构包括具有场氧化物区域的衬底。具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。因此，可以通过断开第二区域来编程半导体熔丝结构。

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