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1. 发明授权

US6093658A Method for making reliable interconnect structures 失效
标题翻译：制造可靠互连结构的方法
公开(公告)号：US6093658A
公开(公告)日：2000-07-25
申请号：US995651
申请日：1997-12-22
申请人： Subhas Bothra , Harlan Lee Sur, Jr. , Victor C. Liang
发明人： Subhas Bothra , Harlan Lee Sur, Jr. , Victor C. Liang
IPC分类号： H01L21/02 , H01L21/311 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L23/522 , H01L21/302
CPC分类号： H01L21/02071 , H01L21/32051 , H01L21/76838 , H01L23/5226 , H01L21/31133 , H01L2924/0002
摘要： Disclosed is a method for making reliable interconnect structures on a semiconductor wafer having a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes exposing the semiconductor wafer to an electron dose that is configured to neutralize the positive charge that is built-up on the at least part of the second metallization layer. The neutralizing is thus configured to substantially prevent tungsten plug erosion.
摘要翻译：公开了一种在具有第一介电层的半导体晶片上制造可靠的互连结构的方法。该方法包括在第一介电层上的等离子体图案化第一金属化层。在第一金属化层和第一介电层上形成第二电介质层。在第二电介质层中形成多个钨塞，使得多个钨塞中的每一个与第一金属化层电接触。等离子体在第二电介质层和多个钨插塞上构图第二金属化层，使得至少一个钨插塞上的至少一个间隙不被第二金属化层覆盖，并且正电荷在第二金属化层的最少部分。该方法还包括将半导体晶片暴露于被配置为中和在第二金属化层的至少部分上积累的正电荷的电子剂量。因此，中和被构造成基本上防止钨插塞侵蚀。

2. 发明授权

US5854510A Low power programmable fuse structures 失效
标题翻译：低功耗可编程保险丝结构
公开(公告)号：US5854510A
公开(公告)日：1998-12-29
申请号：US883403
申请日：1997-06-26
申请人： Harlan Lee Sur, Jr. , Subhas Bothra , Xi-Wei Lin , Martin H. Manley , Robert Payne
发明人： Harlan Lee Sur, Jr. , Subhas Bothra , Xi-Wei Lin , Martin H. Manley , Robert Payne
IPC分类号： H01C13/00 , H01L21/822 , H01L23/525 , H01L27/04 , H01L27/10 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011
摘要： Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.
摘要翻译：公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。熔丝结构包括具有场氧化物区域的衬底。具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。因此，可以通过断开第二区域来编程半导体熔丝结构。

3. 发明授权

US5882998A Low power programmable fuse structures and methods for making the same 失效
标题翻译：低功率可编程熔丝结构及其制造方法
公开(公告)号：US5882998A
公开(公告)日：1999-03-16
申请号：US55018
申请日：1998-04-03
申请人： Harlan Lee Sur, Jr. , Subhas Bothra , Xi-Wei Lin , Martin H. Manley , Robert Payne
发明人： Harlan Lee Sur, Jr. , Subhas Bothra , Xi-Wei Lin , Martin H. Manley , Robert Payne
IPC分类号： H01C13/00 , H01L21/822 , H01L23/525 , H01L27/04 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011
摘要： Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.
摘要翻译：公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。熔丝结构包括具有场氧化物区域的衬底。具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。因此，可以通过断开第二区域来编程半导体熔丝结构。

4. 发明授权

US5764563A Thin film load structure 失效
标题翻译：薄膜负载结构
公开(公告)号：US5764563A
公开(公告)日：1998-06-09
申请号：US723007
申请日：1996-09-30
申请人： Harlan Lee Sur, Jr. , Subhas Bothra
发明人： Harlan Lee Sur, Jr. , Subhas Bothra
IPC分类号： G11C11/412 , H01L21/02 , H01L27/11 , G11C11/00
CPC分类号： H01L28/20 , G11C11/412 , H01L27/1112
摘要： A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.
摘要翻译：用于制造用于集成电路的电阻负载结构的电阻负载结构和方法包括使用非晶硅“反熔丝”材料。电阻负载结构可用于SRAM单元中，以提供负载以抵消SRAM单元的两个下拉晶体管和两个通过晶体管的漏极处的电荷泄漏。有利地通过在导电通孔上沉积非晶硅垫来形成电阻负载结构，并且通过调节非晶硅垫的厚度并改变下面的导电通孔的直径来控制电阻负载结构的电阻。

5. 发明授权

US06277708B1 Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same 失效
标题翻译：用于抑制栅极氧化物等离子体充电损伤的半导体结构及其制造方法
公开(公告)号：US06277708B1
公开(公告)日：2001-08-21
申请号：US09396104
申请日：1999-09-14
申请人： Subhas Bothra , Harlan Lee Sur, Jr.
发明人： Subhas Bothra , Harlan Lee Sur, Jr.
IPC分类号： H01L2176
CPC分类号： H01L21/28525 , H01L21/3065 , H01L21/76224 , H01L21/763 , H01L27/0814 , H01L29/861
摘要： Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.
摘要翻译：公开了半导体二极管结构以及用于制造用于抑制晶体管栅极氧化物等离子体充电损坏的半导体二极管结构的方法。半导体二极管结构包括被配置为隔离半导体衬底的有源区的浅沟槽隔离区。一种具有第一端和第二端的掺杂多晶硅电极。掺杂多晶硅电极限定在浅沟槽隔离区域中，并且第一端被配置为与半导体衬底电接触。二极管结构还包括具有底层栅极氧化物的多晶硅栅极。多晶硅栅极被限定在有源区上并且在浅沟槽隔离区的一部分上延伸，以便在多晶硅栅极和掺杂多晶硅电极的第二端之间形成电互连。

6. 发明授权

US06756316B1 Semiconductor pressure transducer structures and methods for making the same 失效
标题翻译：半导体压力传感器结构及其制造方法
公开(公告)号：US06756316B1
公开(公告)日：2004-06-29
申请号：US09304798
申请日：1999-05-04
申请人： Subhas Bothra , Harlan Lee Sur, Jr.
发明人： Subhas Bothra , Harlan Lee Sur, Jr.
IPC分类号： H01L21302
CPC分类号： B81C1/00047 , B81B2201/0235 , B81B2201/0264 , B81B2207/07 , G01L9/0042
摘要： Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7. In this manner, the tungsten plug will come in direct contact with the basic solution that causes the tungsten plug to be removed while the pressure transducer structure is submerged in the basic solution.
摘要翻译：公开了一种在CMOS集成电路中制造半导体压力传感器结构的方法。该方法包括图案化位于第一氧化物层之上的第一金属化层以产生不与衬底电接触的第一图案化金属化层。在覆盖在第一图案化金属化层上的第二氧化物层中形成钨插塞，使得钨插塞与第一图案化金属化层电接触。将第二金属化层图案化成覆盖在第一图案化金属化层和钨插塞上以产生第二图案化金属化层。第二金属化层的图案化被配置为防止第二图案化金属化层完全覆盖钨插塞。该方法还包括将压力传感器结构浸入具有大于约7的pH水平的碱性溶液中。以这种方式，钨塞将与基本溶液直接接触，导致钨丝塞被去除，而压力传感器结构浸没在基本解决方案中。

7. 发明授权

US5928968A Semiconductor pressure transducer structures and methods for making the same 失效
标题翻译：半导体压力传感器结构及其制造方法
公开(公告)号：US5928968A
公开(公告)日：1999-07-27
申请号：US995500
申请日：1997-12-22
申请人： Subhas Bothra , Harlan Lee Sur, Jr.
发明人： Subhas Bothra , Harlan Lee Sur, Jr.
IPC分类号： B81B3/00 , G01L9/00 , H01L21/00
CPC分类号： B81C1/00047 , G01L9/0042 , B81B2201/0235 , B81B2201/0264 , B81B2207/07
摘要： Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7. In this manner, the tungsten plug will come in direct contact with the basic solution that causes the tungsten plug to be removed while the pressure transducer structure is submerged in the basic solution.
摘要翻译：公开了一种在CMOS集成电路中制造半导体压力传感器结构的方法。该方法包括图案化位于第一氧化物层之上的第一金属化层以产生不与衬底电接触的第一图案化金属化层。在覆盖在第一图案化金属化层上的第二氧化物层中形成钨插塞，使得钨插塞与第一图案化金属化层电接触。将第二金属化层图案化成覆盖在第一图案化金属化层和钨插塞上以产生第二图案化金属化层。第二金属化层的图案化被配置为防止第二图案化金属化层完全覆盖钨插塞。该方法还包括将压力传感器结构浸入具有大于约7的pH水平的碱性溶液中。以这种方式，钨塞将与基本溶液直接接触，导致钨丝塞被去除，而压力传感器结构浸没在基本解决方案中。

8. 发明授权

US6143642A Programmable semiconductor structures and methods for making the same 失效
标题翻译：可编程半导体结构及其制造方法
公开(公告)号：US6143642A
公开(公告)日：2000-11-07
申请号：US995650
申请日：1997-12-22
申请人： Harlan Lee Sur, Jr. , Subhas Bothra
发明人： Harlan Lee Sur, Jr. , Subhas Bothra
IPC分类号： H01L21/768 , H01L23/525 , H01L27/10 , H01L21/4763
CPC分类号： H01L27/10 , H01L21/76888 , H01L23/525 , H01L2924/0002
摘要： Disclosed is a method for making a programmable structure on a semiconductor substrate. The semiconductor structure has a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer. Each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over each of the tungsten plugs is not covered by the second metallization layer. Applying a programming electron dose to a portion of the second metallization layer. The method further includes submersing the semiconductor substrate into a basic solution to remove each of the plurality of tungsten plugs except for a tungsten plug that is in electrical contact with the portion of the second metallization layer that received the applied programming electron dose.
摘要翻译：公开了一种在半导体衬底上制造可编程结构的方法。半导体结构具有第一电介质层。该方法包括在第一介电层上的等离子体图案化第一金属化层。在第一金属化层和第一介电层上形成第二电介质层。在第二电介质层中形成多个钨塞。多个钨插塞中的每一个与第一金属化层电接触。等离子体在第二电介质层和多个钨插塞上图案化第二金属化层，使得每个钨插塞上的至少间隙不被第二金属化层覆盖。对第二金属化层的一部分施加编程电子剂量。该方法还包括将半导体衬底浸入基本溶液中以除去除了接收施加的编程电子剂量的与第二金属化层的部分电接触的钨插塞之外的多个钨插塞中的每一个。

9. 发明授权

US6077762A Method and apparatus for rapidly discharging plasma etched interconnect structures 失效
标题翻译：用于快速放电等离子体蚀刻互连结构的方法和装置
公开(公告)号：US6077762A
公开(公告)日：2000-06-20
申请号：US995652
申请日：1997-12-22
申请人： Victor C. Liang , Subhas Bothra , Harlan Lee Sur, Jr.
发明人： Victor C. Liang , Subhas Bothra , Harlan Lee Sur, Jr.
IPC分类号： H01L21/02 , H01L21/306 , H01L21/3213 , H01L21/768 , H01L21/3205
CPC分类号： H01L21/02071 , H01L21/76838 , H01L21/02052 , H01L21/32136 , Y10S438/906 , Y10S438/972
摘要： Disclosed is a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer. The method includes plasma patterning a first metallization layer that lies over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes contacting the second metallization layer with a conductive liquid that is electrically grounded. In this manner, the positive charge that is built-up on the at least part of the second metallization layer is neutralized to prevent tungsten plug erosion.
摘要翻译：公开了一种在具有第一介电层的半导体衬底上制造可靠的互连结构的方法。该方法包括等离子体图案化位于第一介电层之上的第一金属化层。在第一金属化层和第一介电层上形成第二电介质层。在第二电介质层中形成多个钨塞，使得多个钨塞中的每一个与第一金属化层电接触。等离子体在第二电介质层和多个钨插塞上构图第二金属化层，使得至少一个钨插塞上的至少一个间隙不被第二金属化层覆盖，并且正电荷在第二金属化层的最少部分。该方法还包括使第二金属化层与电接地的导电液接触。以这种方式，积聚在第二金属化层的至少一部分上的正电荷被中和以防止钨插塞侵蚀。

10. 发明授权

US6013927A Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same 失效
标题翻译：用于抑制栅极氧化物等离子体充电损伤的半导体结构及其制造方法
公开(公告)号：US6013927A
公开(公告)日：2000-01-11
申请号：US52859
申请日：1998-03-31
申请人： Subhas Bothra , Harlan Lee Sur, Jr.
发明人： Subhas Bothra , Harlan Lee Sur, Jr.
IPC分类号： H01L21/285 , H01L21/3065 , H01L21/762 , H01L21/763 , H01L27/08 , H01L29/861 , H01L29/76
CPC分类号： H01L21/28525 , H01L21/76224 , H01L21/763 , H01L27/0814 , H01L29/861 , H01L21/3065
摘要： Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.
摘要翻译：公开了半导体二极管结构以及用于制造用于抑制晶体管栅极氧化物等离子体充电损坏的半导体二极管结构的方法。半导体二极管结构包括被配置为隔离半导体衬底的有源区的浅沟槽隔离区。一种具有第一端和第二端的掺杂多晶硅电极。掺杂多晶硅电极限定在浅沟槽隔离区域中，并且第一端被配置为与半导体衬底电接触。二极管结构还包括具有底层栅极氧化物的多晶硅栅极。多晶硅栅极被限定在有源区上并且在浅沟槽隔离区的一部分上延伸，以便在多晶硅栅极和掺杂多晶硅电极的第二端之间形成电互连。

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