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1. 发明授权

US08701054B2 Boosting transistor performance with non-rectangular channels 有权
标题翻译：用非矩形通道提高晶体管的性能
公开(公告)号：US08701054B2
公开(公告)日：2014-04-15
申请号：US13237818
申请日：2011-09-20
申请人： Victor Moroz , Munkang Choi , Xi-Wei Lin
发明人： Victor Moroz , Munkang Choi , Xi-Wei Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L21/266 , H01L27/0207 , H01L29/1033 , H01L29/41758
摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.
摘要翻译：粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

2. 发明申请

US20100187609A1 BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS 审中-公开
标题翻译：提高非矩形通道的晶体管性能
公开(公告)号：US20100187609A1
公开(公告)日：2010-07-29
申请号：US12390338
申请日：2009-02-20
申请人： Victor Moroz , Munkang Choi , Xi-Wei Lin
发明人： Victor Moroz , Munkang Choi , Xi-Wei Lin
IPC分类号： H01L27/088 , G06F17/50 , G03F1/00
CPC分类号： G06F17/5072 , H01L21/266 , H01L27/0207 , H01L29/1033 , H01L29/41758
摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.
摘要翻译：粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

3. 发明申请

US20140167174A1 INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES 有权
标题翻译：在金融和纳米线上增加离子/ IOFF比率
公开(公告)号：US20140167174A1
公开(公告)日：2014-06-19
申请号：US13717532
申请日：2012-12-17
申请人： Munkang Choi , Victor Moroz , Xi-Wei Lin
发明人： Munkang Choi , Victor Moroz , Xi-Wei Lin
IPC分类号： H01L29/78 , H01L21/02
CPC分类号： H01L29/78 , B82Y10/00 , H01L21/02365 , H01L29/0673 , H01L29/42376 , H01L29/66439 , H01L29/775 , H01L29/785 , H01L29/7853 , H01L29/78696
摘要： Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.
摘要翻译：粗略地描述，集成电路晶体管结构具有半导体材料体，该主体具有两个纵向间隔开的掺杂源极/漏极体积，其间具有通道，位于主体外部并面向主体的至少一个表面的栅极堆叠这个频道。主体在通道容积内纵向地包含调节体积，并且在第一表面之后隔开第一距离并且与源/排出体积纵向隔开。调节体积包括至少在晶体管处于截止状态时在每个纵向位置处具有不同于相同主体材料在同一纵向位置的电导率的调节体积材料。在一个实施例中，调节体积材料是电介质。在另一个实施例中，调节体积材料是电导体。

4. 发明申请

US20120011479A1 BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS 有权
标题翻译：提高非矩形通道的晶体管性能
公开(公告)号：US20120011479A1
公开(公告)日：2012-01-12
申请号：US13237818
申请日：2011-09-20
申请人： Victor Moroz , Munkang Choi , Xi-Wei Lin
发明人： Victor Moroz , Munkang Choi , Xi-Wei Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L21/266 , H01L27/0207 , H01L29/1033 , H01L29/41758
摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.
摘要翻译：粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

5. 发明申请

US20110309453A1 ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH ISOLATION ON TRANSISTOR PERFORMANCE 有权
标题翻译：晶体管通道的增加可以减少晶体管性能上的微分离分离的影响
公开(公告)号：US20110309453A1
公开(公告)日：2011-12-22
申请号：US13221747
申请日：2011-08-30
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
摘要翻译：粗略描述，晶体管沟道区域在某些相邻STI区域的水平上升高。优选地，与扩散区横向相邻的STI区域被抑制，与N沟道扩散区域纵向相邻的STI区也是如此。优选地，与P沟道扩散纵向相邻的STI区域不被抑制; 优选地，它们具有至少与扩散区域相同的高度。

6. 发明授权

US07681164B2 Method and apparatus for placing an integrated circuit device within an integrated circuit layout 有权
标题翻译：将集成电路器件放置在集成电路布局内的方法和装置
公开(公告)号：US07681164B2
公开(公告)日：2010-03-16
申请号：US11848524
申请日：2007-08-31
申请人： Xi-Wei Lin , Victor Moroz
发明人： Xi-Wei Lin , Victor Moroz
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation devices within the continuous row of diffusion so that the IC device can be electrically isolated from other IC devices. The system then biases the one or more isolation device so that the IC device is electrically isolated from other IC devices within the continuous row of diffusion.
摘要翻译：提出了一种将集成电路（IC）器件放置在IC芯片布局内的系统。在操作期间，系统接收要放置在IC芯片布局内的IC器件，其中IC芯片布局包括一个或多个连续的扩散行。接下来，系统将IC器件放置在连续的扩散行内。然后，系统确定IC器件是否与其他IC器件电隔离。如果是这样，系统将一个或多个隔离装置插入连续的扩散行内，使得IC器件可以与其它IC器件电隔离。然后，该系统偏置一个或多个隔离装置，使得IC器件与连续的扩散排中的其它IC器件电隔离。

7. 发明授权

US07542891B2 Method of correlating silicon stress to device instance parameters for circuit simulation 有权
标题翻译：将硅应力与电路仿真器件实例参数相关联的方法
公开(公告)号：US07542891B2
公开(公告)日：2009-06-02
申请号：US11470978
申请日：2006-09-07
申请人： Xi-Wei Lin , Victor Moroz , Dipankar Pramanik
发明人： Xi-Wei Lin , Victor Moroz , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.
摘要翻译：粗略描述，可以通过替代不同的应力分析器来更好地模拟晶体管的应力调整特性来修改标准SPICE模型。第一，标准，应力敏感的晶体管模型用于开发第一晶体管性能测量与可用作第二，不应力敏感晶体管模型的输入的一个或多个实例参数之间的数学关系。第二晶体管模型可以例如与第一模型相同，其应力灵敏度被禁用。此后，可以使用替代应力分析器来确定用于第一性能测量的应力调整值，并且可以使用数学关系将该值转换为一个或多个实例参数的特定值。然后将这些值提供给第二晶体管模型，以用于在电路仿真期间模拟特定晶体管的特性。

8. 发明申请

US20070202662A1 Managing integrated circuit stress using dummy diffusion regions 有权
标题翻译：使用虚拟扩散区管理集成电路应力
公开(公告)号：US20070202662A1
公开(公告)日：2007-08-30
申请号：US11364390
申请日：2006-02-27
申请人： Xi-Wei Lin , Dipankar Pramanik , Victor Moroz
发明人： Xi-Wei Lin , Dipankar Pramanik , Victor Moroz
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823814 , H01L29/7846
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

9. 发明授权

US08069430B2 Stress-managed revision of integrated circuit layouts 有权
标题翻译：集成电路布局的压力管理修订
公开(公告)号：US08069430B2
公开(公告)日：2011-11-29
申请号：US12546959
申请日：2009-08-25
申请人： Victor Moroz , Xi-Wei Lin , Dipankar Pramanik
发明人： Victor Moroz , Xi-Wei Lin , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L21/823807
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

10. 发明授权

US07926018B2 Method and apparatus for generating a layout for a transistor 有权
标题翻译：用于产生晶体管布局的方法和装置
公开(公告)号：US07926018B2
公开(公告)日：2011-04-12
申请号：US11860775
申请日：2007-09-25
申请人： Victor Moroz , Xi-Wei Lin , Mark Rubin
发明人： Victor Moroz , Xi-Wei Lin , Mark Rubin
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068
摘要： A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape.
摘要翻译：提出了一种产生晶体管布局的系统。在操作期间，系统接收晶体管库，其包括与晶体管栅极形状相关的制造晶体管的工作特性。该系统还接收晶体管的一个或多个期望的工作特性。接下来，系统基于晶体管库确定用于晶体管的晶体管栅极形状，使得具有晶体管栅极形状的制造晶体管基本上实现一个或多个期望的工作特性。然后，系统产生包括晶体管栅极形状的晶体管的布局。

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