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1. 发明授权

US08664111B2 Method of patterning a semiconductor device with hard mask 有权
标题翻译：用硬掩模图案化半导体器件的方法
公开(公告)号：US08664111B2
公开(公告)日：2014-03-04
申请号：US13249505
申请日：2011-09-30
申请人： Ha-Jin Lim , Moon-Han Park , Eun-Gon Kim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha-Jin Lim , Moon-Han Park , Eun-Gon Kim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/4763
CPC分类号： H01L21/28123 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/32134 , H01L21/32139 , H01L29/517 , H01L29/518
摘要： There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.
摘要翻译：提供了制造半导体器件的方法。在该方法中，在基板上形成包括高k电介质材料的栅极绝缘层。在栅绝缘层上形成蚀刻停止层。在蚀刻停止层上形成金属层。在金属层上形成包括非晶硅的硬掩模。使用硬掩模作为蚀刻掩模对金属层进行图案化以形成金属层图案。

2. 发明授权

US08471359B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08471359B2
公开(公告)日：2013-06-25
申请号：US12656746
申请日：2010-02-16
申请人： Weon-Hong Kim , Min-Woo Song , Jung-Min Park
发明人： Weon-Hong Kim , Min-Woo Song , Jung-Min Park
IPC分类号： H01L29/93
CPC分类号： H01L28/60 , H01L21/02178 , H01L21/02189 , H01L21/022 , H01L21/02274 , H01L21/0228 , H01L21/3142 , H01L21/31604 , H01L21/31641 , H01L27/10852 , H01L28/40
摘要： A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.
摘要翻译：一种包括衬底的半导体器件; 基底上的底电极; 所述第一电介质层包括包含Hf，Al，Zr，La，Ba，Sr，Ti和Pb中的至少一种的第一金属氧化物; 在所述第一电介质层上的第二电介质层，所述第二电介质层包括包含Hf，Al，Zr，La，Ba，Sr，Ti和Pb中的至少一种的第二金属氧化物，其中所述第一金属氧化物和所述第二金属氧化物是不同的材料; 第二电介质层上的第三电介质层，第三电介质层包括金属碳氮氧化物; 以及第三电介质层上的上电极。

3. 发明授权

US07581550B2 Method of cleaning reaction chamber using substrate having catalyst layer thereon 有权
标题翻译：使用其上具有催化剂层的基板清洁反应室的方法
公开(公告)号：US07581550B2
公开(公告)日：2009-09-01
申请号：US11046873
申请日：2005-02-01
申请人： Seok-Jun Won , Weon-Hong Kim , Min-Woo Song
发明人： Seok-Jun Won , Weon-Hong Kim , Min-Woo Song
IPC分类号： B08B9/00 , B08B6/00 , B08B9/093
CPC分类号： H01J37/32862 , B08B7/0035 , C23C16/4405 , C23F4/00 , Y10S134/902 , Y10S438/905 , Y10T428/12528 , Y10T428/24917 , Y10T428/31678
摘要： A method of cleaning a reaction chamber using a substrate having a metal catalyst thereon is disclosed. The method includes preparing a substrate having a catalyst layer to activate a cleaning gas. The substrate is introduced into the reaction chamber. Next, a cleaning gas is introduced into the reaction chamber. Contaminations in the reaction chamber are exhausted. The substrate having a metal catalyst layer is also disclosed.
摘要翻译：公开了一种使用其上具有金属催化剂的基板清洁反应室的方法。该方法包括制备具有催化剂层以激活清洁气体的基材。将基底引入反应室。接下来，将清洁气体引入反应室。反应室内的污染已经耗尽。还公开了具有金属催化剂层的基板。

4. 发明申请

US20080265371A1 Capacitor Unit and Method of Forming the Same 有权
标题翻译：电容器单元及其形成方法
公开(公告)号：US20080265371A1
公开(公告)日：2008-10-30
申请号：US12106830
申请日：2008-04-21
申请人： Jung-Min Park , Seok-Jun Won , Min-Woo Song , Weon-Hong Kim
发明人： Jung-Min Park , Seok-Jun Won , Min-Woo Song , Weon-Hong Kim
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： H01L28/65 , H01G4/33 , H01G4/38 , Y10S438/957
摘要： A capacitor unit includes a first capacitor and a second capacitor. The first capacitor includes a first lower electrode, a first dielectric layer pattern and a first upper electrode sequentially stacked. The first capacitor includes a first control layer pattern for controlling a voltage coefficient of capacitance (VCC) of the first capacitor between the first lower electrode and the first dielectric layer pattern. The second capacitor includes a second lower electrode, a second dielectric layer pattern and a second upper electrode sequentially stacked. The second lower electrode is electrically connected to the first upper electrode, and the second upper electrode is electrically connected to the second lower electrode. The second capacitor includes a second control layer pattern for controlling a VCC of the second capacitor between the second lower electrode and the second dielectric layer pattern.
摘要翻译：电容器单元包括第一电容器和第二电容器。第一电容器包括第一下电极，第一电介质层图案和顺序层叠的第一上电极。第一电容器包括用于控制第一电容器和第一电介质层图案之间的第一电容器的电容电压（VCC）的电压系数的第一控制层图案。第二电容器包括顺序层叠的第二下电极，第二电介质层图案和第二上电极。第二下部电极与第一上部电极电连接，第二上部电极与第二下部电极电连接。第二电容器包括用于在第二下电极和第二电介质层图案之间控制第二电容器的VCC的第二控制层图案。

5. 发明授权

US07435654B2 Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same 有权
标题翻译：具有至少三个高k电介质层的模拟电容器及其制造方法
公开(公告)号：US07435654B2
公开(公告)日：2008-10-14
申请号：US11452828
申请日：2006-06-14
申请人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
发明人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
IPC分类号： H01L21/20 , H01L21/44
CPC分类号： H01L28/40 , H01L21/31637 , H01L21/31645
摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.
摘要翻译：提供了具有至少三个高k电介质层的模拟电容器及其制造方法。模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层为与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

6. 发明申请

US20070026688A1 Method of forming a ZrO2 thin film using plasma enhanced atomic layer deposition and method of fabricating a capacitor of a semiconductor memory device having the thin film 失效
标题翻译：使用等离子体增强原子层沉积法形成ZrO 2薄膜的方法以及制造具有薄膜的半导体存储器件的电容器的方法
公开(公告)号：US20070026688A1
公开(公告)日：2007-02-01
申请号：US11485523
申请日：2006-07-13
申请人： Min-Woo Song , Seok-Jun Won , Weon-Hong Kim , Dae-Jin Kwon , Jung-Min Park
发明人： Min-Woo Song , Seok-Jun Won , Weon-Hong Kim , Dae-Jin Kwon , Jung-Min Park
IPC分类号： H01L21/20 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02189 , C23C16/405 , C23C16/45542 , C23C16/45553 , C23C16/515 , H01L21/022 , H01L21/0228 , H01L21/3141 , H01L21/31641 , H01L27/1085 , H01L28/40
摘要： Example embodiments of the present invention relate to a method of forming a dielectric thin film and a method of fabricating a semiconductor memory device having the same. Other example embodiments of the present invention relate to a method of forming a ZrO2 thin film and a method of fabricating a capacitor of a semiconductor memory device using the ZrO2 thin film as a dielectric layer. A method of forming a ZrO2 thin film may include supplying a zirconium precursor on a substrate maintained at a desired temperature, thereby forming a chemisorption layer of the precursor on the substrate. The zirconium precursor may be a tris(N-ethyl-N-methylamino)(tert-butoxy) zirconium precursor. The substrate having the chemisorption layer of the precursor may be exposed to the plasma atmosphere of oxygen-containing gas for a desired time, thereby forming a Zr oxide layer on the substrate, and a method of fabricating a capacitor of a semiconductor memory device having the ZrO2 thin film.
摘要翻译：本发明的示例性实施例涉及一种形成电介质薄膜的方法及其制造具有该电介质薄膜的半导体存储器件的方法。本发明的其它示例性实施例涉及形成ZrO 2薄膜的方法和使用ZrO 2薄膜的半导体存储器件的电容器的制造方法作为电介质层。形成ZrO 2 H 2薄膜的方法可以包括在保持在所需温度的基板上提供锆前体，由此在基板上形成前体的化学吸附层。锆前体可以是三（N-乙基-N-甲基氨基）（叔丁氧基）锆前体。具有前体的化学吸附层的基板可以暴露于含氧气体的等离子体气氛所需的时间，从而在基板上形成Zr氧化物层，以及制造半导体存储器件的电容器的方法，其具有 ZrO 2薄膜。

7. 发明授权

US07166541B2 Method of forming dielectric layer using plasma enhanced atomic layer deposition technique 失效
标题翻译：使用等离子体增强原子层沉积技术形成介电层的方法
公开(公告)号：US07166541B2
公开(公告)日：2007-01-23
申请号：US11149498
申请日：2005-06-09
申请人： Min-Woo Song , Seok-Jun Won , Yong-Kuk Jeong , Dae-Jin Kwon , Weon-Hong Kim
发明人： Min-Woo Song , Seok-Jun Won , Yong-Kuk Jeong , Dae-Jin Kwon , Weon-Hong Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/02274 , C23C16/405 , C23C16/45542 , H01L21/02175 , H01L21/0228 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645
摘要： A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the reaction chamber; stopping the supply of the source gas and purging the source gas remaining inside the reaction chamber; and supplying oxygen gas into the reaction chamber after purging the source gas, and applying RF power for oxygen plasma treatment, a level of the applied RF power and a partial pressure of the oxygen gas being increased concurrently with an increased aspect ratio of the three-dimensional structure.
摘要翻译：使用等离子体增强原子层沉积技术形成电介质层的方法包括：将具有三维结构的半导体衬底加载到反应室中; 并重复执行以下步骤，直到形成具有所需厚度的电介质层：将源气体供应到反应室中; 停止源气体的供给并清除剩余在反应室内的源气体; 并且在净化源气体之后将氧气供应到反应室中，并施加用于氧等离子体处理的RF功率，所施加的RF功率的水平和氧气的分压同时增加，尺寸结构。

8. 发明申请

US20060234466A1 Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same 有权
标题翻译：具有至少三个高k电介质层的模拟电容器及其制造方法
公开(公告)号：US20060234466A1
公开(公告)日：2006-10-19
申请号：US11452828
申请日：2006-06-14
申请人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
发明人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L21/31637 , H01L21/31645
摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.
摘要翻译：提供了具有至少三个高k电介质层的模拟电容器及其制造方法。模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

9. 发明申请

US20060215348A1 MEMS tunable capacitor with a wide tuning range 有权
标题翻译：具有宽调谐范围的MEMS可调电容器
公开(公告)号：US20060215348A1
公开(公告)日：2006-09-28
申请号：US11444357
申请日：2006-06-01
申请人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
发明人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
IPC分类号： H01G5/00
CPC分类号： H01G5/0136 , H01G5/14 , H01G5/145 , H01G5/18
摘要： A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
摘要翻译： MEMS可调谐电容器及其制造方法包括在基板上的多个固定的充电板，多个具有相同高度的固定充电板被布置成梳齿形并彼此电连接，覆盖所述多个固定充电板的电容器电介质层，与所述电容器介电层间隔开并且布置在所述多个固定的充电板上的可移动的充电板结构，其中所述可移动的充电板结构包括多个相应地布置的可移动的充电板多个固定的充电板和连接到可移动的充电板结构的致动器，其允许可移动的充电板结构在水平方向上移动。

10. 发明授权

US07091548B2 Analog capacitor having at least three high-k-dielectric layers, and method of fabricating the same 有权
标题翻译：具有至少三个高k电介质层的模拟电容器及其制造方法
公开(公告)号：US07091548B2
公开(公告)日：2006-08-15
申请号：US10874461
申请日：2004-06-23
申请人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
发明人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L21/31637 , H01L21/31645
摘要： There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.
摘要翻译：提供了具有至少三个高k电介质层的模拟电容器及其制造方法。模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

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