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1. 发明申请

US20070106833A1 Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
标题翻译：可扩展分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US20070106833A1
公开(公告)日：2007-05-10
申请号：US11422542
申请日：2006-06-06
申请人： Linda Rankin , Paul Pierce , Gregory Dermer , Wen-Hann Wang , Kai Cheng , Richard Hofsheier , Nitin Borkar
发明人： Linda Rankin , Paul Pierce , Gregory Dermer , Wen-Hann Wang , Kai Cheng , Richard Hofsheier , Nitin Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥接器。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

2. 发明申请

US20080114919A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US20080114919A1
公开(公告)日：2008-05-15
申请号：US12013595
申请日：2008-01-14
申请人： Linda Rankin , Paul Pierce , Gregory Dermer , Wen-Hann Wang , Kai Cheng , Richard Hofsheier , Nitin Borkar
发明人： Linda Rankin , Paul Pierce , Gregory Dermer , Wen-Hann Wang , Kai Cheng , Richard Hofsheier , Nitin Borkar
IPC分类号： G06F13/36
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

3. 发明申请

US20120317328A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统
公开(公告)号：US20120317328A1
公开(公告)日：2012-12-13
申请号：US13590936
申请日：2012-08-21
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

4. 发明授权

US07930464B2 Scalable memory and I/O multiprocessor systems 有权
标题翻译：可扩展内存和I / O多处理器系统
公开(公告)号：US07930464B2
公开(公告)日：2011-04-19
申请号：US12549491
申请日：2009-08-28
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

5. 发明授权

US08745306B2 Scalable distributed memory and I/O multiprocessor system 有权
标题翻译：可扩展分布式内存和I / O多处理器系统
公开(公告)号：US08745306B2
公开(公告)日：2014-06-03
申请号：US13590936
申请日：2012-08-21
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

6. 发明授权

US07058750B1 Scalable distributed memory and I/O multiprocessor system 有权
标题翻译：可扩展分布式内存和I / O多处理器系统
公开(公告)号：US07058750B1
公开(公告)日：2006-06-06
申请号：US09569100
申请日：2000-05-10
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥接器。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

7. 发明授权

US08255605B2 Scalable distributed memory and I/O multiprocessor system 有权
标题翻译：可扩展分布式内存和I / O多处理器系统
公开(公告)号：US08255605B2
公开(公告)日：2012-08-28
申请号：US13076041
申请日：2011-03-30
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BICS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

8. 发明申请

US20090319717A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US20090319717A1
公开(公告)日：2009-12-24
申请号：US12549491
申请日：2009-08-28
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

9. 发明授权

US07603508B2 Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
标题翻译：可扩展分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US07603508B2
公开(公告)日：2009-10-13
申请号：US12013595
申请日：2008-01-14
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

10. 发明授权

US07343442B2 Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
标题翻译：可扩展分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US07343442B2
公开(公告)日：2008-03-11
申请号：US11422542
申请日：2006-06-06
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

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