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1. 发明授权

US08907340B2 Semiconductor arrangement with an integrated hall sensor 有权
标题翻译：半导体布置与集成霍尔传感器
公开(公告)号：US08907340B2
公开(公告)日：2014-12-09
申请号：US13241627
申请日：2011-09-23
申请人： Franz Hirler , Walter Rieger , Lutz Goergens , Helmut Angerer , Gianmauro Pozzovivo , Markus Zundel
发明人： Franz Hirler , Walter Rieger , Lutz Goergens , Helmut Angerer , Gianmauro Pozzovivo , Markus Zundel
IPC分类号： H01L23/58 , H01L27/06 , B82Y10/00 , H01L27/22 , H01L43/06 , H01L29/778
CPC分类号： B82Y10/00 , H01L27/0617 , H01L27/22 , H01L29/7787 , H01L43/065
摘要： A semiconductor arrangement includes a semiconductor body and a semiconductor device, the semiconductor device including first and second load terminals arranged distant to each other in a first direction of the semiconductor body and a load path arranged in the semiconductor body between the first and second load terminals. The semiconductor arrangement further includes at least one Hall sensor arranged in the semiconductor body distant to the semiconductor device in a second direction perpendicular to the first direction. The Hall sensor includes two current supply terminals and two measurement terminals.
摘要翻译：半导体装置包括半导体本体和半导体器件，所述半导体器件包括在所述半导体本体的第一方向上彼此远离布置的第一和第二负载端子以及布置在所述半导体本体中的所述第一和第二负载端子之间的负载路径。半导体装置还包括至少一个霍尔传感器，该霍尔传感器在垂直于第一方向的第二方向上布置在远离半导体器件的半导体本体中。霍尔传感器包括两个电源端子和两个测量端子。

2. 发明授权

US08314447B2 Semiconductor including lateral HEMT 有权
标题翻译：半导体包括横向HEMT
公开(公告)号：US08314447B2
公开(公告)日：2012-11-20
申请号：US12764669
申请日：2010-04-21
申请人： Franz Hirler , Walter Rieger , Markus Zundel
发明人： Franz Hirler , Walter Rieger , Markus Zundel
IPC分类号： H01L29/739
CPC分类号： H01L29/778 , H01L29/0619 , H01L29/0623 , H01L29/0653 , H01L29/1075 , H01L29/2003 , H01L29/402 , H01L29/41766 , H01L29/66462 , H01L29/7786
摘要： A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.
摘要翻译：公开了包括横向HEMT的半导体和用于制造横向HEMT的方法。在一个实施例中，横向HEMT具有衬底和第一层，其中第一层具有第一导电类型的半导体材料并且至少部分地布置在衬底上。此外，横向HEMT具有第二层，其中第二层具有半导体材料并且至少部分地布置在第一层上。此外，横向HEMT具有第三层，其中第三层具有与第一导电类型互补的第二导电类型的半导体材料，并且至少部分地布置在第一层中。

3. 发明申请

US20120028417A1 SEMICONDUCTOR COMPONENT WITH CELL STRUCTURE AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：具有细胞结构的半导体元件及其制造方法
公开(公告)号：US20120028417A1
公开(公告)日：2012-02-02
申请号：US13268097
申请日：2011-10-07
申请人： Franz Hirler , Oliver Haeberlen , Walter Rieger
发明人： Franz Hirler , Oliver Haeberlen , Walter Rieger
IPC分类号： H01L21/78
CPC分类号： H01L29/7802 , H01L23/4824 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7397 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode.
摘要翻译：半导体部件包括半导体本体，其包括布置在半导体主体的一个表面上的第一部件电极，布置在半导体主体的一个表面上的第二部件电极和布置在半导体主体的一个表面上的部件控制电极半导体体。在这种情况下，有源半导体元件单元被布置在半导体本体的第一有源单元阵列中，半导体元件单元包括第一单元电极，第二单元电极和单元控制电极，以及单元电极之间的漂移路径。至少部件控制电极布置在半导体本体的部分区域上，并且第二有源电池阵列另外位于半导体本体的部件控制电极下方的部分区域中。

4. 发明授权

US08044459B2 Semiconductor device with trench field plate including first and second semiconductor materials 有权
标题翻译：具有沟槽场板的半导体器件包括第一和第二半导体材料
公开(公告)号：US08044459B2
公开(公告)日：2011-10-25
申请号：US12268182
申请日：2008-11-10
申请人： Franz Hirler , Walter Rieger , Andrew Wood , Mathias Born , Ralf Siemieniec , Jan Ropohl , Martin Poelzl , Oliver Blank , Uli Hiller , Oliver Haeberlen , Rudolf Zelsacher , Maximilian Roesch , Joachim Krumrey
发明人： Franz Hirler , Walter Rieger , Andrew Wood , Mathias Born , Ralf Siemieniec , Jan Ropohl , Martin Poelzl , Oliver Blank , Uli Hiller , Oliver Haeberlen , Rudolf Zelsacher , Maximilian Roesch , Joachim Krumrey
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material.
摘要翻译：在一个实施例中，场效应晶体管具有半导体本体，第一导电类型的漂移区和栅电极。至少一个沟槽延伸到漂移区域中。至少在所述至少一个沟槽的一部分中布置场板。绝缘材料至少部分地围绕栅电极和场板两者。场板包括第一半导体材料。

5. 发明授权

US07999287B2 Lateral HEMT and method for the production of a lateral HEMT 有权
标题翻译：横向HEMT和生产横向HEMT的方法
公开(公告)号：US07999287B2
公开(公告)日：2011-08-16
申请号：US12605751
申请日：2009-10-26
申请人： Markus Zundel , Franz Hirler , Walter Rieger
发明人： Markus Zundel , Franz Hirler , Walter Rieger
IPC分类号： H01L29/66
CPC分类号： H01L29/404 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： In one embodiment a lateral HEMT has a first layer, the first layer including a semiconducting material, and a second layer, the second layer including a semiconducting material and being at least partially arranged on the first layer. The lateral HEMT further has a passivation layer and a drift region, the drift region including a lateral width wd. The lateral HEMT further has at least one field plate, the at least one field plate being arranged at least partially on the passivation layer in a region of the drift region and including a lateral width wf, wherein wf
摘要翻译：在一个实施例中，横向HEMT具有第一层，第一层包括半导体材料和第二层，第二层包括半导体材料并且至少部分地布置在第一层上。横向HEMT还具有钝化层和漂移区域，漂移区域包括横向宽度wd。横向HEMT还具有至少一个场板，所述至少一个场板至少部分地布置在所述漂移区域的区域中的钝化层上，并且包括横向宽度wf，其中wf

6. 发明授权

US07833862B2 Semiconductor device and method for forming same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US07833862B2
公开(公告)日：2010-11-16
申请号：US12041391
申请日：2008-03-03
申请人： Oliver Blank , Uli Hiller , Maximilian Roesch , Walter Rieger
发明人： Oliver Blank , Uli Hiller , Maximilian Roesch , Walter Rieger
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66734
摘要： A semiconductor device and method. One embodiments provides a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material, a field electrode formed in lower portion of the trench, a cover comprising a second material above the field electrode, the second material being selectively etchable to the first isolating material, a gate dielectric on the sidewall in an upper portion of the trench and a gate electrode in the upper portion of the trench.
摘要翻译：半导体器件和方法。一个实施例提供了具有沟槽的半导体衬底，侧壁隔离包括第一隔离材料，形成在沟槽下部的场电极，覆盖在场电极上方的第二材料，第二材料可选择性地蚀刻到第一隔离材料，在沟槽的上部中的侧壁上的栅极电介质和沟槽上部的栅电极。

7. 发明申请

US20090114986A1 FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT 有权
标题翻译：现场平板晶体管及其生产方法
公开(公告)号：US20090114986A1
公开(公告)日：2009-05-07
申请号：US12349952
申请日：2009-01-07
申请人： Franz Hirler , Walter Rieger , Thorsten Meyer , Wolfgang Klein , Frank Pfirsch
发明人： Franz Hirler , Walter Rieger , Thorsten Meyer , Wolfgang Klein , Frank Pfirsch
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L27/04 , H01L27/0727 , H01L29/0696 , H01L29/0878 , H01L29/404 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/732 , H01L29/735 , H01L29/7803 , H01L29/7808 , H01L29/861
摘要： A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
摘要翻译：具有半导体本体的场板沟槽晶体管。在一个实施例中，半导体具有沟槽结构和嵌入沟槽结构中的电极结构。电极结构通过绝缘结构与半导体本体电绝缘并具有栅电极结构和场电极结构。场板沟槽晶体管具有分压器，其被配置为使得场电极结构被设置为位于源极和漏极之间的电位。

8. 发明授权

US07250343B2 Power transistor arrangement and method for fabricating it 有权
标题翻译：功率晶体管布置及其制造方法
公开(公告)号：US07250343B2
公开(公告)日：2007-07-31
申请号：US10987189
申请日：2004-11-12
申请人： Manfred Kotek , Oliver Häberlen , Martin Pölzl , Walter Rieger
发明人： Manfred Kotek , Oliver Häberlen , Martin Pölzl , Walter Rieger
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41741 , H01L29/4238 , H01L29/7811
摘要： In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).
摘要翻译：在根据本发明的用于制造功率晶体管布置的成本有效的方法的情况下，制造具有四个图案平面的沟槽功率晶体管布置（1），每个图案平面包含光刻步骤。根据本发明的功率晶体管装置具有一个具有单元阵列沟槽（5）的单元阵列（3），每个单元阵列具有场电极结构（11）和栅电极结构（10）。场电极结构（11）通过电池阵列（3）中的连接沟槽（6）与源极金属化（15）导电连接。

9. 发明申请

US20070093019A1 Method for producing a connection electrode for two semiconductor zones arranged one above another 有权
标题翻译：一种制造用于两个半导体区域的连接电极的方法，所述半导体区域布置在另一个之上
公开(公告)号：US20070093019A1
公开(公告)日：2007-04-26
申请号：US11527743
申请日：2006-09-26
申请人： Walter Rieger , Paul Ganitzer , Oliver Haeberlen , Franz Hirler , Markus Zundel , Rudolf Zelsacher , Erwin Bacher
发明人： Walter Rieger , Paul Ganitzer , Oliver Haeberlen , Franz Hirler , Markus Zundel , Rudolf Zelsacher , Erwin Bacher
IPC分类号： H01L21/8242 , H01L21/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/086 , H01L29/0869 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7397
摘要： Method for producing a connection electrode for two semiconductor zones arranged one above another The invention relates to a method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone, which are arranged one above another and are doped complementarily with respect to one another, which method comprises the method steps of: producing a trench extending through the first semiconductor zone right into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench, applying a protective layer to one of the first and second semiconductor zones in the trench, producing a first connection zone in the other of the two semiconductor zones, which is not covered by the protective layer, by introducing dopant atoms into this other semiconductor zone via the trench, the connection zone being of the same conductivity type as said other semiconductor zone, but doped more highly, depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode.
摘要翻译：一种制造用于两个半导体区域的连接电极的方法本发明涉及一种用于制造用于第一半导体区域和第二半导体区域的连接电极的方法，所述连接电极被布置在另一个之上，并且相对于一个另一方面，该方法包括以下方法步骤：产生通过第一半导体区域直接进入第二半导体区域的沟槽，使得第一半导体区域在沟槽的侧壁处未被覆盖，并且至少覆盖第二半导体区域在沟槽的底部，在沟槽中的第一和第二半导体区域中的一个上施加保护层，在两个半导体区域中的另一个半导体区域中的第一连接区域中，未被保护层覆盖，通过引入掺杂剂原子通过沟槽进入该另一半导体区，连接区具有相同的导电性类型作为所述另一半导体区，但是掺杂更高，至少在沟槽的侧壁和底部上沉积电极层以产生连接电极。

10. 发明申请

US20060097312A1 Method for producing a vertical transistor component 有权
标题翻译：垂直晶体管部件的制造方法
公开(公告)号：US20060097312A1
公开(公告)日：2006-05-11
申请号：US11241867
申请日：2005-09-30
申请人： Martin Poelzl , Walter Rieger
发明人： Martin Poelzl , Walter Rieger
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/66719 , H01L29/66734 , H01L29/7805
摘要： The invention relates to a method for producing a vertical transistor component, having the following method steps of: Providing a semiconductor substrate (100), applying an auxiliary layer (110) to the semiconductor substrate (100), patterning the auxiliary layer (110) for the purpose of producing at least one trench (114) which extends as far as the semiconductor substrate (100) and which has opposite sidewalls (115), producing a monocrystalline semiconductor layer (132) on at least one of the sidewalls (115) of the trench (114), producing an electrode (140) insulated from the monocrystalline semiconductor layer (132) on the at least one sidewall (115) of the trench (114) and the semiconductor substrate (100). The invention furthermore relates to a method for producing a vertical transistor component, having the following method steps of: Providing a semiconductor substrate (200), applying an auxiliary layer (210) to the semiconductor substrate (200), patterning the auxiliary layer (210) for the purpose of producing at least one trench (214) which extends as far as the semiconductor substrate (200), producing a monocrystalline semiconductor zone (230) in the at least one trench (213), removing the auxiliary layer (210) at least in sections, producing an electrode (240) insulated from the monocrystalline semiconductor zone (230) and the semiconductor substrate.
摘要翻译：本发明涉及一种用于制造垂直晶体管部件的方法，具有以下方法步骤：提供半导体衬底（100），向半导体衬底（100）施加辅助层（110），使辅助层（110）构图，为了产生至少一个延伸到半导体衬底（100）并且具有相对侧壁（115）的沟槽（114）的目的，在至少一个侧壁（115）上产生单晶半导体层（132）在沟槽（114）和半导体衬底（100）的至少一个侧壁（115）上产生与单晶半导体层（132）绝缘的电极（140）。本发明还涉及一种用于制造垂直晶体管部件的方法，具有以下方法步骤：提供半导体衬底（200），向半导体衬底（200）施加辅助层（210），使辅助层（210）），用于产生延伸到半导体衬底（200）的至少一个沟槽（214），在至少一个沟槽（213）中产生单晶半导体区（230），去除辅助层（210）至少在部分中产生与单晶半导体区（230）和半导体衬底绝缘的电极（240）。

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