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1. 发明授权

US09373688B2 Normally-off high electron mobility transistors 有权
标题翻译：常关高电子迁移率晶体管
公开(公告)号：US09373688B2
公开(公告)日：2016-06-21
申请号：US13100343
申请日：2011-05-04
申请人： Gilberto Curatola , Oliver Häberlen , Gianmauro Pozzovivo
发明人： Gilberto Curatola , Oliver Häberlen , Gianmauro Pozzovivo
IPC分类号： H01L29/778 , H01L29/66 , H01L29/423 , H01L29/43 , H01L29/20
CPC分类号： H01L29/42356 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/66462 , H01L29/7786
摘要： A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.
摘要翻译：常闭晶体管包括III-V族半导体材料的第一区域，第一区域上的III-V族半导体材料的第二区域，第二区域上的III-V族半导体材料的第三区域和至少相邻的栅电极第三区域的一个侧壁。第一区域提供晶体管的通道。第二区域具有比第一区域的带隙大的带隙，并且在通道中产生2-D电子气体（2DEG）。第二区域介于第一区域和第三区域之间。第三区域提供晶体管的栅极并且具有足以消耗沟道中的2DEG的厚度，使得晶体管具有正的阈值电压。

2. 发明授权

US08569799B2 III-V semiconductor devices with buried contacts 有权
标题翻译：具有埋地触点的III-V半导体器件
公开(公告)号：US08569799B2
公开(公告)日：2013-10-29
申请号：US13331899
申请日：2011-12-20
申请人： Gilberto Curatola , Guanmauro Pozzovivo , Oliver Häberlen
发明人： Gilberto Curatola , Guanmauro Pozzovivo , Oliver Häberlen
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L21/743 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/66143 , H01L29/66462 , H01L29/872
摘要： A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate.
摘要翻译：诸如二极管或晶体管的半导体器件包括半导体衬底，半导体衬底上的III-V半导体材料的第一区域和第一区域上的III-V半导体材料的第二区域。第二区域与第一区域与半导体衬底间隔开。第二区域具有与第一区域不同的组成。半导体器件还包括从半导体衬底延伸穿过第一区域延伸到第二区域的埋入触点。埋入式触点将第二区域电连接到半导体衬底。

3. 发明授权

US08872235B2 Integrated Schottky diode for HEMTs 有权
标题翻译：用于HEMT的集成肖特基二极管
公开(公告)号：US08872235B2
公开(公告)日：2014-10-28
申请号：US13403606
申请日：2012-02-23
申请人： Gerhard Prechtl , Clemens Ostermaier , Oliver Häberlen
发明人： Gerhard Prechtl , Clemens Ostermaier , Oliver Häberlen
IPC分类号： H01L29/66
CPC分类号： H01L29/66462 , H01L21/283 , H01L21/32055 , H01L29/2003 , H01L29/452 , H01L29/66143 , H01L29/7786 , H01L29/872
摘要： An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device.
摘要翻译：晶体管器件的一个实施例包括半导体载体上的化合物半导体材料和在化合物半导体材料中彼此间隔开的源极区和漏极区，其中介于源极和漏极区之间的沟道区。肖特基二极管与半导体载体集成，并且触点从源区和漏区延伸穿过化合物半导体材料。触点与肖特基二极管电接触，使得肖特基二极管并联连接在源区和漏区之间。在另一个实施例中，集成肖特基二极管由设置在器件漏极侧的沟槽结构中的掺杂非晶硅或掺杂多晶硅的区域形成。

4. 发明授权

US08587033B1 Monolithically integrated HEMT and current protection device 有权
标题翻译：单片集成HEMT和电流保护装置
公开(公告)号：US08587033B1
公开(公告)日：2013-11-19
申请号：US13487795
申请日：2012-06-04
申请人： Walter Rieger , Oliver Häberlen
发明人： Walter Rieger , Oliver Häberlen
IPC分类号： H01L29/66
CPC分类号： H01L29/778 , H01L27/0248 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/42364 , H01L29/7786 , H01L2924/0002 , H02M1/32 , H02M3/1588 , Y02B70/1466 , H01L2924/00
摘要： A transistor device includes a high electron mobility field effect transistor (HEMT) and a protection device. The HEMT has a source, a drain and a gate. The HEMT switches on and conducts current from the source to the drain when a voltage applied to the gate exceeds a threshold voltage of the HEMT. The protection device is monolithically integrated with the HEMT so that the protection device shares the source and the drain with the HEMT and further includes a gate electrically connected to the source. The protection device conducts current from the drain to the source when the HEMT is switched off and a reverse voltage between the source and the drain exceeds a threshold voltage of the protection device. The protection device has a lower threshold voltage than the difference of the threshold voltage of the HEMT and a gate voltage used to turn off the HEMT.
摘要翻译：晶体管器件包括高电子迁移率场效应晶体管（HEMT）和保护器件。 HEMT有一个源头，一个排水沟和一个门。当施加到栅极的电压超过HEMT的阈值电压时，HEMT接通并导通从源极到漏极的电流。保护装置与HEMT单片集成，使得保护装置与HEMT共享源极和漏极，并且还包括电连接到源极的栅极。当HEMT关闭时，保护装置将电流从漏极传导到源极，并且源极和漏极之间的反向电压超过保护器件的阈值电压。保护装置具有比HEMT的阈值电压和用于关断HEMT的栅极电压的差值更低的阈值电压。

5. 发明申请

US20130299842A1 Contact Structures for Compound Semiconductor Devices 有权
标题翻译：复合半导体器件的接触结构
公开(公告)号：US20130299842A1
公开(公告)日：2013-11-14
申请号：US13470771
申请日：2012-05-14
申请人： Gerhard Prechtl , Clemens Ostermaier , Oliver Häberlen , Gianmauro Pozzovivo
发明人： Gerhard Prechtl , Clemens Ostermaier , Oliver Häberlen , Gianmauro Pozzovivo
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/778 , H01L21/28575 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/66431 , H01L29/66462 , H01L29/7786
摘要： A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.
摘要翻译：半导体器件包括半导体本体，其包括多个化合物半导体层和形成在化合物半导体层之一中的二维电荷载流子通道区域。半导体器件还包括设置在半导体本体中的接触结构。接触结构包括金属区域和掺杂区域。金属区域从半导体本体的第一侧延伸到半导体本体至少包括沟道区的化合物半导体层。掺杂区域形成在金属区域和沟道区域之间的半导体本体中，使得沟道区域通过掺杂区域电连接到金属区域。

6. 发明申请

US20140042448A1 High Breakdown Voltage III-Nitride Device 有权
标题翻译：高击穿电压III-Nitride器件
公开(公告)号：US20140042448A1
公开(公告)日：2014-02-13
申请号：US13584442
申请日：2012-08-13
申请人： Clemens Ostermaier , Gerhard Prechtl , Oliver Häberlen
发明人： Clemens Ostermaier , Gerhard Prechtl , Oliver Häberlen
IPC分类号： H01L29/778 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7787 , H01L21/7605 , H01L21/76224 , H01L21/76264 , H01L21/76283 , H01L23/481 , H01L29/0642 , H01L29/0649 , H01L29/0653 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/66462 , H01L29/7783 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor body having a compound semiconductor material on a substrate. The compound semiconductor material has a channel region. A source region extends to the compound semiconductor material. A drain region also extends to the compound semiconductor material and is spaced apart from the source region by the channel region. An insulating region is buried in the semiconductor body between the compound semiconductor material and the substrate in an active region of the semiconductor device. The active region includes the source, the drain and the channel region of the device. The insulating region is discontinuous over a length of the channel region between the source region and the drain region.
摘要翻译：半导体器件包括在衬底上具有化合物半导体材料的半导体本体。化合物半导体材料具有沟道区域。源极区延伸到化合物半导体材料。漏极区域还延伸到化合物半导体材料并且通过沟道区域与源极区域间隔开。在半导体器件的有源区域中，绝缘区域埋在化合物半导体材料和衬底之间的半导体本体中。有源区包括器件的源极，漏极和沟道区域。绝缘区域在源极区域和漏极区域之间的沟道区域的长度上是不连续的。

7. 发明授权

US08586993B2 Normally-off compound semiconductor tunnel transistor 有权
标题翻译：常规化合物半导体隧道晶体管
公开(公告)号：US08586993B2
公开(公告)日：2013-11-19
申请号：US13406568
申请日：2012-02-28
申请人： Gilberto Curatola , Oliver Häberlen
发明人： Gilberto Curatola , Oliver Häberlen
IPC分类号： H01L29/778
CPC分类号： H01L29/7788 , H01L21/0254 , H01L29/2003 , H01L29/267 , H01L29/401 , H01L29/66431 , H01L29/7391 , H01L29/7783 , H01L29/7786
摘要： Disclosed herein are embodiments of a normally-off compound semiconductor tunnel field effect transistor having a drive current above 100 mA per mm of gate length and a sub-threshold slope below 60 mV per decade at room temperature, and methods of manufacturing such a normally-off compound semiconductor tunnel transistor. The compound semiconductor tunnel field effect transistor is fast-switching and can be used for high voltage applications e.g. 30V up to 600V and higher.
摘要翻译：本文公开了常温化合物半导体隧道场效应晶体管的实施例，其具有每毫米栅极长度高于100mA的驱动电流和在室温下每十年低于60mV的次阈值斜率的制造方法，关闭复合半导体隧道晶体管。化合物半导体隧道场效应晶体管是快速切换的，并且可以用于高电压应用，例如 30V至600V及以上。

8. 发明申请

US20120280278A1 Normally-Off High Electron Mobility Transistors 有权
标题翻译：常关高电子迁移率晶体管
公开(公告)号：US20120280278A1
公开(公告)日：2012-11-08
申请号：US13100343
申请日：2011-05-04
申请人： Gilberto Curatola , Oliver Häberlen , Gianmauro Pozzovivo
发明人： Gilberto Curatola , Oliver Häberlen , Gianmauro Pozzovivo
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/42356 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/66462 , H01L29/7786
摘要： A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.
摘要翻译：常闭晶体管包括III-V族半导体材料的第一区域，第一区域上的III-V族半导体材料的第二区域，第二区域上的III-V族半导体材料的第三区域和至少相邻的栅电极第三区域的一个侧壁。第一区域提供晶体管的通道。第二区域具有比第一区域的带隙大的带隙，并且在通道中产生2-D电子气体（2DEG）。第二区域介于第一区域和第三区域之间。第三区域提供晶体管的栅极并且具有足以消耗沟道中的2DEG的厚度，使得晶体管具有正的阈值电压。

9. 发明授权

US07186618B2 Power transistor arrangement and method for fabricating it 有权
标题翻译：功率晶体管布置及其制造方法
公开(公告)号：US07186618B2
公开(公告)日：2007-03-06
申请号：US10977118
申请日：2004-10-29
申请人： Martin Pölzl , Franz Hirler , Oliver Häberlen , Manfred Kotek , Walter Rieger
发明人： Martin Pölzl , Franz Hirler , Oliver Häberlen , Manfred Kotek , Walter Rieger
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4238 , H01L29/7811
摘要： When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.
摘要翻译：当制造具有有源电池阵列沟槽（5）和无源连接沟槽（6）的沟槽功率晶体管布置（1）时，电池阵列沟槽（5）的宽度大于连接沟槽（6）。辅助层（24）保形地沉积在单元阵列沟槽（5）和连接沟槽（6）中的下部电场结构（11）上并被回蚀到连接沟槽（6）中的顶部边缘，，其从单元阵列沟槽（5）中移除它。辅助层（24）允许栅极氧化物（20）被图案化而不需要复杂的掩模工艺。在场电极结构（11）的电位上具有电极的边缘沟槽（7）将电池阵列（3）与漏极电势屏蔽。

10. 发明授权

US06649459B2 Method for manufacturing a semiconductor component 有权
标题翻译：半导体部件的制造方法
公开(公告)号：US06649459B2
公开(公告)日：2003-11-18
申请号：US09817594
申请日：2001-03-26
申请人： Gerald Deboy , Wolfgang Friza , Oliver Häberlen , Michael Rüb , Helmut Strack
发明人： Gerald Deboy , Wolfgang Friza , Oliver Häberlen , Michael Rüb , Helmut Strack
IPC分类号： H01L21338
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/41766
摘要： The invention relates to a method for producing a semiconductor component including semiconductor areas of different conductivity types which are alternately positioned in a semiconductor body. The semiconductor areas of different conductivity types extend at least from one first zone to a position near a second zone. Because of variable doping in trenches and in the trench fillings, an electric field is generated which increases from both the first zone and the second zone.
摘要翻译：本发明涉及一种用于制造半导体元件的方法，该半导体元件包括交替地位于半导体本体中的不同导电类型的半导体区域。不同导电类型的半导体区域至少从一个第一区延伸到靠近第二区的位置。由于沟槽和沟槽填充中的可变掺杂，产生从第一区和第二区两者增加的电场。

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