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1. 发明申请

WO2011051015A3 ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT 审中-公开
标题翻译：含门槛电压的铝金属门槛
公开(公告)号：WO2011051015A3
公开(公告)日：2011-10-20
申请号：PCT/EP2010062579
申请日：2010-08-27
申请人： IBM , IBM UK , WONG KEITH KWONG HON , GUO DECHAO , KWON UNOH , WANG YUN-YU , PARKS CHRISTOPHER CARR
发明人： WONG KEITH KWONG HON , GUO DECHAO , KWON UNOH , WANG YUN-YU , PARKS CHRISTOPHER CARR
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51
CPC分类号： H01L29/511 , H01L21/28079 , H01L21/28088 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.
摘要翻译：提供了一种形成p型半导体器件的方法，其在一个实施例中采用含铝阈值电压偏移层来产生朝向p型半导体器件的价带的阈值电压偏移。形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极介电层，存在于栅极介电层上的含铝阈值电压偏移层，以及与含铝阈值电压偏移层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区域可以形成在衬底的与其上存在栅极结构的部分相邻的衬底中。还提供了由上述方法提供的p型半导体器件。

2. 发明申请

WO2007039385A1 METAL INTERCONNECT STRUCTURE FOR A MICROELECTRONIC ELEMENT 审中-公开
标题翻译：微电子元件的金属互连结构
公开(公告)号：WO2007039385A1
公开(公告)日：2007-04-12
申请号：PCT/EP2006/066077
申请日：2006-09-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , YANG, Chih-Chao , CHANDA, Kaushik , CLEVENGER, Lawrence , WANG, Yun-Yu , YANG, Daewon
发明人： YANG, Chih-Chao , CHANDA, Kaushik , CLEVENGER, Lawrence , WANG, Yun-Yu , YANG, Daewon
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/76832 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.
摘要翻译：提供了互连结构及其制造方法。互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

3. 发明申请

WO2006029950A1 UNI-DIRECTIONAL DIFFUSION OF METAL SILICIDE IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：金属硅化物在半导体器件中的单向扩散
公开(公告)号：WO2006029950A1
公开(公告)日：2006-03-23
申请号：PCT/EP2005/054087
申请日：2005-08-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , DOMENICUCCI, Anthony , JONES, Bradley , LAVOIE, Christian , PURTELL, Robert , WANG, Yun Yu , WONG, Kwong Hon
发明人： DOMENICUCCI, Anthony , JONES, Bradley , LAVOIE, Christian , PURTELL, Robert , WANG, Yun Yu , WONG, Kwong Hon
IPC分类号： H01L21/285
CPC分类号： H01L21/28518 , H01L29/665
摘要： The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy (56) in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer (52) . The first thermal cycle causes an amorphous metal-containing silicide (60) to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide (64) that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide (68) phase that is in its lowest resistance phase. A metal silicide is provided whose thicknes is self-limiting.
摘要翻译：本发明提供一种通过使用含金属的硅合金（56）与进行两个不同的热循环的第一退火相结合来增强硅化物中金属的单向扩散的方法。第一退火的第一热循环在能够增强金属例如Co和/或Ni的单向扩散到含Si层（52）中的温度下进行。第一热循环导致形成非晶态金属的硅化物（60）。第二热循环在将含非晶态金属的硅化物转化为与含金属的硅合金层或纯金属含有层相比基本上不可蚀刻的结晶的富含金属的硅化物（64）的温度下进行。在第一退火之后，进行选择性蚀刻以从结构中除去任何未反应的含金属合金。执行第二退火以将由第一退火的两个热循环形成的富金属硅化物相转换成处于其最低电阻相的金属硅化物（68）相。提供了一种金属硅化物，其厚度是自限制的。

4. 发明申请

WO2004027824A3 NITRIDE AND POLYSILICON INTERFACE WITH TITANIUM LAYER 审中-公开
公开(公告)号：WO2004027824A3
公开(公告)日：2004-04-01
申请号：PCT/US2003/029085
申请日：2003-09-16
申请人： INFINEON TECHNOLOGIES AG , INTERNATIONAL BUSINESS MACHINES CORP. , SCHUTZ, Ronald, J. , ROBL, Werner , MALIK, Rajeev , CLEVENGER, Larry , GLUSCHENKOV, Oleg , CABRAL, Cyril, Jr. , IGGULDEN, Roy, C. , WANG, Yun-Yu , WONG, Kwong, Hon , MCSTAY, Irene
发明人： SCHUTZ, Ronald, J. , ROBL, Werner , MALIK, Rajeev , CLEVENGER, Larry , GLUSCHENKOV, Oleg , CABRAL, Cyril, Jr. , IGGULDEN, Roy, C. , WANG, Yun-Yu , WONG, Kwong, Hon , MCSTAY, Irene
IPC分类号： H01L21/4763
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

5. 发明申请

WO2004027824A2 NITRIDE AND POLYSILICON INTERFACE WITH TITANIUM LAYER 审中-公开
标题翻译：氮化钛和多晶硅界面与钛层
公开(公告)号：WO2004027824A2
公开(公告)日：2004-04-01
申请号：PCT/US0329085
申请日：2003-09-16
申请人： INFINEON TECHNOLOGIES AG , IBM , SCHUTZ RONALD J , ROBL WERNER , MALIK RAJEEV , CLEVENGER LARRY , GLUSCHENKOV OLEG , CABRAL CYRIL JR , IGGULDEN ROY C , WANG YUN-YU , WONG KWONG HON , MCSTAY IRENE
发明人： SCHUTZ RONALD J , ROBL WERNER , MALIK RAJEEV , CLEVENGER LARRY , GLUSCHENKOV OLEG , CABRAL CYRIL JR , IGGULDEN ROY C , WANG YUN-YU , WONG KWONG HON , MCSTAY IRENE
IPC分类号： H01L20060101 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L23/522 , H01L29/40 , H01L29/51 , H01L29/78 , H01L
CPC分类号： H01L21/7685 , H01L21/28052 , H01L21/28061 , H01L21/76838 , H01L21/76855 , H01L21/823828 , H01L21/823842 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L2221/1078
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要翻译：提供了集成电路（12）中的导电结构以及形成该结构的方法，该导电结构包括多晶硅层（30），在多晶硅上包含钛的薄层，在钛 - 氮化镓层上的氮化钨层（34）在氮化钨层上形成含钨层和钨层。该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。该结构耐受高温处理而在多晶硅层（30）和钨层（32）中基本上不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

6. 发明申请

WO2011051015A2 ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT 审中-公开
标题翻译：用于阈值电压转换的包含金属层的铝
公开(公告)号：WO2011051015A2
公开(公告)日：2011-05-05
申请号：PCT/EP2010/062579
申请日：2010-08-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , WONG, Keith, Kwong Hon , GUO, Dechao , KWON, Unoh , WANG, Yun-Yu , PARKS, Christopher, Carr
发明人： WONG, Keith, Kwong Hon , GUO, Dechao , KWON, Unoh , WANG, Yun-Yu , PARKS, Christopher, Carr
IPC分类号： H01L21/28 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L29/511 , H01L21/28079 , H01L21/28088 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.
摘要翻译：提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层以产生朝向p型半导体器件的价带的阈值电压偏移。形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层，以及与含铝的阈值电压偏移层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区域可以形成在与存在栅极结构的衬底的部分相邻的衬底中。还提供了通过上述方法提供的p型半导体器件。

7. 发明申请

WO2008060745A1 INTERCONNECT STRUCTURE HAVING ENHANCED ELECTROMIGRATION RELIABILITY AND A METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有增强电化学可靠性的互连结构及其制造方法
公开(公告)号：WO2008060745A1
公开(公告)日：2008-05-22
申请号：PCT/US2007/077975
申请日：2007-09-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-Chao , WANG, Ping-Chuan , WANG, Yun-Yu
发明人： YANG, Chih-Chao , WANG, Ping-Chuan , WANG, Yun-Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76847 , H01L23/5226 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner (66) at least partially within a metal interconnect. In one embodiment, a "U-shaped" EM preventing liner (66) is provided that abuts a diffusion barrier that separates conductive material (64, 68) from the dielectric material (54B). In another embodiment, a space is located between the "U-shaped" EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.
摘要翻译：提供了具有改进的电迁移（EM）可靠性的互连结构。本发明的互连结构通过至少部分地在金属互连内并入EM防护衬套（66）来避免由EM故障引起的电路死路。在一个实施例中，提供了一个“U形”EM防护衬套（66），其邻接将导电材料（64,68）与电介质材料（54B）分离的扩散阻挡层。在另一个实施例中，空间位于“U形”EM防护衬垫和扩散阻挡层之间。在另一个实施例中，提供了一个与扩散阻挡件相邻的水平EM衬垫。在又一个实施例中，在水平EM衬垫和扩散阻挡层之间存在一个空间。

8. 发明申请

WO2007136907A3 COMPRESSIVE NITRIDE FILM AND METHOD OF MANUFACTURING THEREOF 审中-公开
公开(公告)号：WO2007136907A3
公开(公告)日：2007-11-29
申请号：PCT/US2007/063377
申请日：2007-03-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Daewon , LEE, Woo-Hyeong , SU, Tai-chi , WANG, Yun-yu
发明人： YANG, Daewon , LEE, Woo-Hyeong , SU, Tai-chi , WANG, Yun-yu
IPC分类号： H01L21/31 , B05D3/00
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8W/cm 2 and 5.0W/cm 2 ; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

9. 发明申请

WO2007136907A2 COMPRESSIVE NITRIDE FILM AND METHOD OF MANUFACTURING THEREOF 审中-公开
标题翻译：压电式薄膜及其制造方法
公开(公告)号：WO2007136907A2
公开(公告)日：2007-11-29
申请号：PCT/US2007063377
申请日：2007-03-06
申请人： IBM , YANG DAEWON , LEE WOO-HYEONG , SU TAI-CHI , WANG YUN-YU
发明人： YANG DAEWON , LEE WOO-HYEONG , SU TAI-CHI , WANG YUN-YU
IPC分类号： H01L21/31 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/3185 , C23C16/345 , C23C16/505 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8W/cm 2 and 5.0W/cm 2 ; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.
摘要翻译：本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

10. 发明申请

WO2005024906A3 STRUCTURE AND METHOD FOR METAL REPLACEMENT GATE OF HIGH PERFORMANCE DEVICE 审中-公开
公开(公告)号：WO2005024906A3
公开(公告)日：2005-03-17
申请号：PCT/US2004/027327
申请日：2004-08-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , WANG, Yun-Yu , STEEGEN, An, L. , KU, Victor , WONG, Kwong, Hon , LI, Ying , NARAYANAN, Vijay , CABRAL Cyril, Jr. , JAMISON, Paul
发明人： STEEGEN, An, L. , KU, Victor , WONG, Kwong, Hon , LI, Ying , NARAYANAN, Vijay , CABRAL Cyril, Jr. , JAMISON, Paul
IPC分类号： H01L29/94
摘要： A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

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