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1. 发明授权

US08407499B2 Optimizing power management in partitioned multicore virtual machine platforms by uniform distribution of a requested power reduction between all of the processor cores 失效
标题翻译：通过在所有处理器内核之间均匀分配所需的功耗，优化分区多核虚拟机平台中的电源管理
公开(公告)号：US08407499B2
公开(公告)日：2013-03-26
申请号：US12763431
申请日：2010-04-20
申请人： Vaijayanthimala K Anand , Diane Garza Flemming , William A Maron , Mysore Srinivas
发明人： Vaijayanthimala K Anand , Diane Garza Flemming , William A Maron , Mysore Srinivas
IPC分类号： G06F1/32 , G06F1/24 , G06F9/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F9/5077 , G06F9/5094 , Y02D10/126 , Y02D10/22 , Y02D10/36
摘要： Handling requests for power reduction by first enabling a request for an amount of power change, e.g. reduction by any partition. In response to the request for power reduction, an equal proportion of the whole amount of power reduction is distributed between each of a set of cores providing the entitlements to the partitions, and the entitlement of the requesting partition is reduced by an amount corresponding to the whole amount of the power change.
摘要翻译：通过首先启用功率变化量的请求来处理功率降低的请求，例如，减少任何分区。响应于减少功率的请求，在提供分配权利的一组核心的每一个之间分配全部功率减少的相等比例，并且请求分区的授权减少对应于整个功率的变化量。

2. 发明授权

US07865895B2 Heuristic based affinity dispatching for shared processor partition dispatching 有权
标题翻译：用于共享处理器分区调度的基于启发式的亲和性调度
公开(公告)号：US07865895B2
公开(公告)日：2011-01-04
申请号：US11419019
申请日：2006-05-18
申请人： Vaijayanthimala K. Anand , Dean J. Burdick , Bret R. Olszewski
发明人： Vaijayanthimala K. Anand , Dean J. Burdick , Bret R. Olszewski
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/5033 , G06F9/5077 , G06F2209/508
摘要： A mechanism is provided for determining whether to use cache affinity as a criterion for software thread dispatching in a shared processor logical partitioning data processing system. The server firmware may store data about when and/or how often logical processors are dispatched. Given these data, the operating system may collect metrics. Using the logical processor metrics, the operating system may determine whether cache affinity is likely to provide a significant performance benefit relative to the cost of dispatching a particular logical processor to the operating system.
摘要翻译：提供了一种用于确定是否使用高速缓存亲和力作为在共享处理器逻辑分区数据处理系统中的软件线程调度的标准的机制。服务器固件可以存储关于何时和/或多少逻辑处理器被调度的数据。鉴于这些数据，操作系统可能会收集指标。使用逻辑处理器度量，操作系统可以确定高速缓存关联性是否可能相对于将特定逻辑处理器调度到操作系统的成本提供显着的性能优点。

3. 发明申请

US20100274938A1 PERIPHERAL ADAPTER INTERRUPT FREQUENCY CONTROL BY ESTIMATING PROCESSOR LOAD AT THE PERIPHERAL ADAPTER 有权
标题翻译：通过外围适配器估计处理器负载的外设适配器中断频率控制
公开(公告)号：US20100274938A1
公开(公告)日：2010-10-28
申请号：US12550309
申请日：2009-08-28
申请人： Vaijayanthimala K. Anand , Janice Marie Girouard , Emily Jane Ratliff
发明人： Vaijayanthimala K. Anand , Janice Marie Girouard , Emily Jane Ratliff
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F3/00 , H04L12/56
摘要： Interrupt frequency control by estimating processor load in the peripheral adapter provides adaptive interrupt latency to improve performance in a processing system. A mathematical function of the depth of one or more queues of the adapter is compared to its historical value in order to provide an estimate of processor load. The estimated processor load is then used to set a parameter that controls the frequency of an interrupt generator, which may be controlled by setting an interrupt queue depth threshold, packet frequency threshold or interrupt hold-off time value. The mathematical function may be the ratio of the transmit queue depth to the receive queue depth and the historical value may be predetermined, user-settable, obtained during a calibration interval or obtained by taking a long-term average of the mathematical function of the queue depths.
摘要翻译：中断频率控制通过估计外设适配器中的处理器负载提供自适应中断延迟，以提高处理系统的性能。将适配器的一个或多个队列的深度的数学函数与其历史值进行比较，以提供处理器负载的估计。然后，估计的处理器负载用于设置控制中断发生器频率的参数，该参数可以通过设置中断队列深度阈值，分组频率阈值或中断缓存时间值来控制。数学函数可以是发送队列深度与接收队列深度的比率，并且历史值可以是预定的，用户可设置的，在校准间隔期间获得或通过取得队列的数学函数的长期平均值获得深度。

4. 发明申请

US20100115522A1 MECHANISM TO CONTROL HARDWARE MULTI-THREADED PRIORITY BY SYSTEM CALL 有权
标题翻译：通过系统呼叫控制硬件多线程优先级的机制
公开(公告)号：US20100115522A1
公开(公告)日：2010-05-06
申请号：US12261275
申请日：2008-10-30
申请人： Vaijayanthimala K. Anand , Joerg Droste , Bruce Mealey , Bret R. Olszewski
发明人： Vaijayanthimala K. Anand , Joerg Droste , Bruce Mealey , Bret R. Olszewski
IPC分类号： G06F9/46 , G06F15/00
CPC分类号： G06F9/485 , G06F9/4881 , Y02D10/24
摘要： A method, a system and a computer program product for controlling the hardware priority of hardware threads in a data processing system. A Thread Priority Control (TPC) utility assigns a primary level and one or more secondary levels of hardware priority to a hardware thread. When a hardware thread initiates execution in the absence of a system call, the TPC utility enables execution based on the primary level. When the hardware thread initiates execution within a system call, the TPC utility dynamically adjusts execution from the primary level to the secondary level associated with the system call. The TPC utility adjusts hardware priority levels in order to: (a) raise the hardware priority of one hardware thread relative to another; (b) reduce energy consumed by the hardware thread; and (c) fulfill requirements of time critical hardware sections.
摘要翻译：一种用于控制数据处理系统中硬件线程的硬件优先级的方法，系统和计算机程序产品。线程优先级控制（TPC）实用程序为硬件线程分配一级和一级以上的硬件优先级。当硬件线程在没有系统调用的情况下启动执行时，TPC实用程序将启用基于主级别的执行。当硬件线程在系统调用中启动执行时，TPC实用程序会将执行从主级别动态调整到与系统调用相关联的辅助级别。 TPC实用程序调整硬件优先级，以便：（a）提高一个硬件线程相对于另一个的硬件优先级; （b）减少硬件螺纹消耗的能量; 和（c）满足时间关键硬件部分的要求。

5. 发明授权

US06684327B1 Extensible, flexible, memory efficient technique for network boot without special DHCP/PXE hardware 有权
标题翻译：可扩展，灵活，内存高效的网络引导技术，无需特殊的DHCP / PXE硬件
公开(公告)号：US06684327B1
公开(公告)日：2004-01-27
申请号：US09735590
申请日：2000-12-12
申请人： Vaijayanthimala K. Anand , Steven Michael French , James Richard Schoech
发明人： Vaijayanthimala K. Anand , Steven Michael French , James Richard Schoech
IPC分类号： G06F9445
CPC分类号： G06F9/4416
摘要： A method, system, and program for network booting of a client computer is provided. The method comprises loading a special local bootstrap into a client computer and then using this special local bootstrap to save the client Interrupt Vector Table (IVT) to high memory and then passing control to a normal DOS bootstrap. From here a normal DOS boot is performed using files that contain pointers to the drivers of a network device which enables a specific network interface card. A special program is loaded which emulates a PXE application program interface and initiates a DHCP/PXE boot request to the network. In this manner, a client is able to perform a DHCP/PXE boot without specialized hardware, by relying on a software emulation of the necessary DHCP/PXE functions.
摘要翻译：提供了一种用于客户端计算机的网络引导的方法，系统和程序。该方法包括将特殊的本地引导加载到客户端计算机中，然后使用此特殊本地引导将客户端中断向量表（IVT）保存到高内存，然后将控制权传递到正常的DOS引导。从这里，使用包含指向启用特定网络接口卡的网络设备的驱动程序的指针的文件执行正常的DOS引导。加载了一个特殊程序，用于模拟PXE应用程序接口，并向网络发起DHCP / PXE引导请求。以这种方式，客户端可以通过依靠必需的DHCP / PXE功能的软件仿真来执行没有专用硬件的DHCP / PXE引导。

6. 发明授权

US08930670B2 Partition redispatching using page tracking 有权
标题翻译：使用页面跟踪进行分区重新分配
公开(公告)号：US08930670B2
公开(公告)日：2015-01-06
申请号：US11936456
申请日：2007-11-07
申请人： Vaijayanthimala K. Anand , Bret R. Olszewski , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Bret R. Olszewski , Mysore Sathyanarayana Srinivas
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/1009 , G06F2212/401
摘要： Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss in response to determining the page address miss in a page addressing buffer, and saving the mapping as an entry in an array. The computer implemented method creates a preserved array from the array in response to determining the dispatched partition to be an undispatched partition. The computer implemented method further analyzes of the preserved array for a compressed page in response to determining the undispatched partition is now redispatched, and decompresses the compressed page prior to the partition being redispatched.
摘要翻译：说明的实施例提供了一种计算机实现的方法和数据处理系统，用于通过跟踪属于所分派的分区的一组存储器页来重新分配分区。在一个说明性实施例中，计算机实现的方法包括响应于确定页寻址缓冲器中的页面地址未命中而找到页面地址未命中的实际页面地址映射的有效页面地址，并将映射保存为阵列中的条目。计算机实现的方法从数组中创建一个保留的数组，以响应将分派的分区确定为未分配的分区。计算机实现的方法进一步分析压缩页面的保留数组，以响应确定未分配的分区现在被重新分配，并在重新分配分区之前解压缩压缩页面。

7. 发明申请

US20130346967A1 Determining Placement Fitness For Partitions Under A Hypervisor 有权
公开(公告)号：US20130346967A1
公开(公告)日：2013-12-26
申请号：US13529790
申请日：2012-06-21
申请人： Vaijayanthimala K. Anand , Richard Mankowski , Bret R. Olszewski , Sergio Reyes
发明人： Vaijayanthimala K. Anand , Richard Mankowski , Bret R. Olszewski , Sergio Reyes
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F9/45533 , G06F9/5077 , G06F2009/4557 , G06F2009/45583
摘要： A technique for determining placement fitness for partitions under a hypervisor in a host computing system having non-uniform memory access (NUMA) nodes. In an embodiment, a partition resource specification is received from a partition score requester. The partition resource specification identifies a set of computing resources needed for a virtual machine partition to be created by a hypervisor in the host computing system. Resource availability within the NUMA nodes of the host computing system is assessed to determine possible partition placement options. A partition fitness score of a most suitable one of the partition placement options is calculated. The partition fitness score is reported to the partition score requester.

8. 发明授权

US08392659B2 Extending cache capacity on multiple-core processor systems 有权
标题翻译：在多核处理器系统上扩展缓存容量
公开(公告)号：US08392659B2
公开(公告)日：2013-03-05
申请号：US12612767
申请日：2009-11-05
申请人： Vaijayanthimala K. Anand , Diane Garza Flemming , William A. Maron , Mysore Sathyanarayana Srinivas
发明人： Vaijayanthimala K. Anand , Diane Garza Flemming , William A. Maron , Mysore Sathyanarayana Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F2212/601
摘要： A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.
摘要翻译：提供了一种编程介质和系统，用于通过使用同一芯片上的禁用或非使能内核的高速缓存来实现内核的高速缓存容量的增加。对芯片上的禁用或非启用内核的缓存进行访问，以存储已启用的那些芯片内核的高速缓存线，从而扩展启用核心的高速缓存容量。

9. 发明授权

US08301840B2 Assigning cache priorities to virtual/logical processors and partitioning a cache according to such priorities 失效
标题翻译：将缓存优先级分配给虚拟/逻辑处理器，并根据这些优先级对高速缓存进行分区
公开(公告)号：US08301840B2
公开(公告)日：2012-10-30
申请号：US12637891
申请日：2009-12-15
申请人： Vaijayanthimala K. Anand , Diane G. Flemming , William A. Maron , Mysore S. Srinivas
发明人： Vaijayanthimala K. Anand , Diane G. Flemming , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/12
CPC分类号： G06F12/0895 , G06F9/5022 , G06F9/5077 , G06F12/126 , G06F2209/5021
摘要： Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.
摘要翻译：提供了用于在具有至少一个物理处理器和至少一个相关联的高速缓冲存储器的数据处理系统中实现的机制，用于将至少一个高速缓冲存储器的高速缓存资源分配给数据处理系统的虚拟处理器。该机制识别数据处理系统中的多个高优先级虚拟处理器。这些机制进一步确定要分配给高优先级虚拟处理器的至少一个高速缓冲存储器的高速缓存行的百分比。此外，机制将所述至少一个高速缓冲存储器中的高速缓存行的一部分标记为仅基于所分配给高优先级虚拟处理器的高速缓存行的确定百分比仅被高优先级的虚拟处理器驱逐。高速缓存行的标记部分不能被优先级低于高优先级虚拟处理器的较低优先级的虚拟处理器驱逐。

10. 发明授权

US08156498B2 Optimization of thread wake up for shared processor partitions 有权
标题翻译：为共享处理器分区优化线程唤醒
公开(公告)号：US08156498B2
公开(公告)日：2012-04-10
申请号：US12130064
申请日：2008-05-30
申请人： Vaijayanthimala K. Anand , Dean J. Burdick , Bret R. Olszewski
发明人： Vaijayanthimala K. Anand , Dean J. Burdick , Bret R. Olszewski
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/5033 , G06F9/5077
摘要： A mechanism is provided for biasing placement of a software thread on a currently idle and dispatched processor. The operating system starts with the last logical processor on which the software thread ran and determines whether that processor is idle and dispatched and considers each logical processor until a currently dispatched and idle logical processor is found. If a currently dispatched and idle logical processor is not found, then the operating system biases placing the software thread on an idle logical processor.
摘要翻译：提供了一种用于偏置软件线程在当前空闲和调度的处理器上的布置的机制。操作系统从软件线程运行的最后一个逻辑处理器开始，并确定该处理器是否空闲和调度，并考虑每个逻辑处理器，直到找到当前调度和空闲的逻辑处理器。如果没有找到当前调度和空闲的逻辑处理器，则操作系统偏置将软件线程放置在空闲逻辑处理器上。

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