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1. 发明授权

US08610252B2 Scribe line structure for wafer dicing 有权
标题翻译：晶圆切片的划线结构
公开(公告)号：US08610252B2
公开(公告)日：2013-12-17
申请号：US13193612
申请日：2011-07-29
申请人： Ping-Chang Wu , Tsung-Shu Lin
发明人： Ping-Chang Wu , Tsung-Shu Lin
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/78 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer.
摘要翻译：根据本发明的用于晶片切割的划线结构包括在电介质层中的衬底上下设置的多个金属结构，并且上部金属结构具有比下部金属密度低金属结构。另一方面，用于晶片切割的划线结构包括在电介质层中的衬底上下设置的多个金属结构，并且每个金属结构在用于晶片切割的切割路径上具有较低的金属密度不是在切割路径上。划线结构可以有效地避免切割过程，特别是在低k / Cu晶片上造成的层间分层或剥离问题。

2. 发明授权

US08519535B2 Method and structure for controlling package warpage 有权
标题翻译：控制包装翘曲的方法和结构
公开(公告)号：US08519535B2
公开(公告)日：2013-08-27
申请号：US13105360
申请日：2011-05-11
申请人： Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
发明人： Tsung-Shu Lin , Yuh Chern Shieh , Kuo-Chin Chang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/562 , H01L23/3157 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15321 , H01L2924/3511 , H01L2924/00
摘要： A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.
摘要翻译：一种方法包括确定集成电路（IC）封装设计的翘曲。 IC封装设计包括在第一主表面上具有顶部焊接掩模的基板和与第一主表面相对的第二主表面上的底部焊接掩模。第一主表面上安装有IC芯片，顶部焊接掩模。该设计被修改，包括修改由顶部焊接掩模和底部焊接掩模组成的组中的一个的平均厚度，以便减少翘曲。根据改进的设计制造IC封装。

3. 发明授权

US08476759B2 Electrical connection structure 有权
标题翻译：电气连接结构
公开(公告)号：US08476759B2
公开(公告)日：2013-07-02
申请号：US13308249
申请日：2011-11-30
申请人： Yao-Chun Chuang , Chang-Chia Huang , Tsung-Shu Lin , Chen-Cheng Kuo , Chen-Shien Chen
发明人： Yao-Chun Chuang , Chang-Chia Huang , Tsung-Shu Lin , Chen-Cheng Kuo , Chen-Shien Chen
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L23/293 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03462 , H01L2224/0401 , H01L2224/05005 , H01L2224/05022 , H01L2224/05086 , H01L2224/05091 , H01L2224/05124 , H01L2224/05541 , H01L2224/05572 , H01L2224/1145 , H01L2224/11462 , H01L2224/13022 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/206 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2224/05552
摘要： A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.
摘要翻译：结构包括形成在接合焊盘下方的顶部金属连接器。接合焊盘由第一钝化层和第二钝化层包围。聚合物层进一步形成在第二钝化层上。第一钝化层中的开口的尺寸小于顶部金属连接器的尺寸。顶部金属连接器的尺寸小于第二钝化层中的开口的尺寸和聚合物层中的开口的尺寸。

4. 发明申请

US20130127045A1 MECHANISMS FOR FORMING FINE-PITCH COPPER BUMP STRUCTURES 有权
标题翻译：形成精细铜板结构的机理
公开(公告)号：US20130127045A1
公开(公告)日：2013-05-23
申请号：US13406270
申请日：2012-02-27
申请人： Tsung-Shu LIN , Han-Ping PU , Ming-Da CHENG , Chang-Chia HUANG , Hao-Juin LIU
发明人： Tsung-Shu LIN , Han-Ping PU , Ming-Da CHENG , Chang-Chia HUANG , Hao-Juin LIU
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L23/293 , H01L21/568 , H01L23/3157 , H01L24/02 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05541 , H01L2224/05572 , H01L2224/05647 , H01L2224/10126 , H01L2224/1146 , H01L2224/1147 , H01L2224/1181 , H01L2224/1191 , H01L2224/13005 , H01L2224/13007 , H01L2224/13022 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13164 , H01L2224/16237 , H01L2224/73104 , H01L2224/81193 , H01L2224/81411 , H01L2224/81413 , H01L2224/81416 , H01L2224/81439 , H01L2224/81447 , H01L2224/81455 , H01L2924/00014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/206 , H01L2924/207 , H01L2924/01082 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.
摘要翻译：形成所述铜柱结构的机理使得能够在平坦的导电表面上形成铜柱结构。此外，铜柱结构由比聚酰亚胺高的杨氏模量（或更硬的材料）的模制层支撑。形成的铜柱结构大大降低了钝化层开裂的危险和铜柱结构周围介质界面的分层。

5. 发明申请

US20130127040A1 DIE CARRIER FOR PACKAGE ON PACKAGE ASSEMBLY 有权
标题翻译：用于包装组件的包装盒
公开(公告)号：US20130127040A1
公开(公告)日：2013-05-23
申请号：US13302059
申请日：2011-11-22
申请人： Tsung-Shu Lin , Yu-Ling Tsai , Han-Ping Pu
发明人： Tsung-Shu Lin , Yu-Ling Tsai , Han-Ping Pu
IPC分类号： H01L23/485 , B23K1/00 , B23K1/20 , B23K31/12
CPC分类号： H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/1017 , H01L2225/1041 , H01L2225/1058 , H01L2924/00012
摘要： A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.
摘要翻译：提供了一种用于在回流操作期间维持管芯对准的封装封装布置。第一顶模具有焊料凸块的第一布置。底部封装具有电连接到第一焊料凸点布置的第一电气布置。模具载体具有限定在其底表面上的多个安装区域，其中第一顶模在多个安装区域中的第一个处粘附到模具载体。具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。焊料凸块的第一和第二布置彼此对称，其中在回流操作期间平衡表面张力，并且通常相对于底部封装固定模具载体的取向。

6. 发明授权

US07871860B1 Method of semiconductor packaging 有权
标题翻译：半导体封装方法
公开(公告)号：US07871860B1
公开(公告)日：2011-01-18
申请号：US12620321
申请日：2009-11-17
申请人： Han-Ping Pu , Tsung-Shu Lin , Chen-Shien Chen
发明人： Han-Ping Pu , Tsung-Shu Lin , Chen-Shien Chen
IPC分类号： H01L21/00 , H01L21/50 , H01L21/48 , H01L21/44 , H01L21/46
CPC分类号： H01L24/81 , H01L21/563 , H01L24/16 , H01L2224/73203 , H01L2224/81211 , H01L2224/81801 , H01L2924/01006 , H01L2924/01019 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H01L2924/00
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a chip and a substrate. The method also includes bonding the chip to the substrate. The method also includes, after the bonding the chip, dispensing a sealing material between the chip and the substrate. In accordance with the method, the chip and the substrate are maintained within a temperature range from the bonding the chip to the dispensing the sealing material, and wherein a lower limit of the temperature range is approximately twice a room temperature.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供芯片和基板。该方法还包括将芯片接合到衬底。该方法还包括在粘合芯片之后，在芯片和基板之间分配密封材料。根据该方法，将芯片和基板保持在从接合芯片到分配密封材料的温度范围内，并且其中温度范围的下限约为室温的两倍。

7. 发明申请

US20090283869A1 Scribe line structure for wafer dicing and method of making the same 有权
标题翻译：用于晶片切割的划线结构及其制造方法
公开(公告)号：US20090283869A1
公开(公告)日：2009-11-19
申请号：US12119502
申请日：2008-05-13
申请人： Ping-Chang Wu , Tsung-Shu Lin
发明人： Ping-Chang Wu , Tsung-Shu Lin
IPC分类号： H01L23/544 , H01L21/44
CPC分类号： H01L23/544 , H01L21/78 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer.
摘要翻译：根据本发明的用于晶片切割的划线结构包括在电介质层中的衬底上下设置的多个金属结构，并且上部金属结构具有比下部金属密度低金属结构。另一方面，用于晶片切割的划线结构包括在电介质层中的衬底上上下配置的多个金属结构，并且每个金属结构在用于晶片切割的切割路径上具有较低的金属密度不是在切割路径上。划线结构可以有效地避免切割过程，特别是在低k / Cu晶片上造成的层间分层或剥离问题。

8. 发明授权

US09978656B2 Mechanisms for forming fine-pitch copper bump structures 有权
公开(公告)号：US09978656B2
公开(公告)日：2018-05-22
申请号：US13406270
申请日：2012-02-27
申请人： Tsung-Shu Lin , Han-Ping Pu , Ming-Da Cheng , Chang-Chia Huang , Hao-Juin Liu
发明人： Tsung-Shu Lin , Han-Ping Pu , Ming-Da Cheng , Chang-Chia Huang , Hao-Juin Liu
IPC分类号： H01L23/00 , H01L23/29 , H01L23/31 , H01L21/56
CPC分类号： H01L23/293 , H01L21/568 , H01L23/3157 , H01L24/02 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05541 , H01L2224/05572 , H01L2224/05647 , H01L2224/10126 , H01L2224/1146 , H01L2224/1147 , H01L2224/1181 , H01L2224/1191 , H01L2224/13005 , H01L2224/13007 , H01L2224/13022 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13164 , H01L2224/16237 , H01L2224/73104 , H01L2224/81193 , H01L2224/81411 , H01L2224/81413 , H01L2224/81416 , H01L2224/81439 , H01L2224/81447 , H01L2224/81455 , H01L2924/00014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/206 , H01L2924/207 , H01L2924/01082 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.

9. 发明授权

US09887144B2 Ring structure for chip packaging 有权
公开(公告)号：US09887144B2
公开(公告)日：2018-02-06
申请号：US13227983
申请日：2011-09-08
申请人： Wen-Yi Lin , Yu-Chih Liu , Ming-Chih Yew , Tsung-Shu Lin , Bor-Rung Su , Jing Ruei Lu , Wei-Ting Lin
发明人： Wen-Yi Lin , Yu-Chih Liu , Ming-Chih Yew , Tsung-Shu Lin , Bor-Rung Su , Jing Ruei Lu , Wei-Ting Lin
IPC分类号： H01L23/10 , H01L23/16 , H01L23/36 , H01L21/56 , H01L23/00
CPC分类号： H01L23/10 , H01L21/563 , H01L23/16 , H01L23/36 , H01L24/16 , H01L24/32 , H01L24/33 , H01L2224/131 , H01L2224/16225 , H01L2224/29099 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.

10. 发明授权

US09548283B2 Package redistribution layer structure and method of forming same 有权
标题翻译：包装再分配层结构及其形成方法
公开(公告)号：US09548283B2
公开(公告)日：2017-01-17
申请号：US13542528
申请日：2012-07-05
申请人： Tsung-Shu Lin , Hung-Jui Kuo , Yi-Wen Wu
发明人： Tsung-Shu Lin , Hung-Jui Kuo , Yi-Wen Wu
IPC分类号： H01L29/49 , H01L23/00 , H01L23/538 , H01L25/10 , H01L23/31 , H01L25/16
CPC分类号： H01L24/73 , H01L23/3121 , H01L23/5389 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/107 , H01L2924/0002 , H01L2924/1461 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the substrate. The PoP device further comprises a top package over the bottom package and a redistribution layer coupling the top package to the substrate. A method of forming a PoP device comprises coupling a first package to a substrate; and forming a redistribution layer over the first package and a top surface of the substrate. The method further comprises coupling a second package to the redistribution layer, wherein the redistribution layer couples the second package to the substrate.
摘要翻译：封装封装（PoP）器件包括在衬底上的底部封装和耦合底部封装和衬底的第一组导电元件。 PoP器件还包括在底部封装上的顶部封装以及将顶部封装耦合到衬底的再分配层。形成PoP器件的方法包括将第一封装耦合到衬底; 以及在所述第一封装和所述衬底的顶表面上形成再分布层。该方法还包括将第二包装物耦合到再分配层，其中再分配层将第二包装物耦合到基底。

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