专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06962140B1 Diesel engine control system and control method 有权
标题翻译：柴油机控制系统及控制方法
公开(公告)号：US06962140B1
公开(公告)日：2005-11-08
申请号：US10656100
申请日：2003-09-08
申请人： Eiji Nakai , Naoki Okada , Tsunehiro Sato , Yoshiyuki Matsumoto , Masami Nakao , Masanori Sahara , Kouji Habu , Hiromu Sugano , Masaru Yamamoto , Tunehiro Mori
发明人： Eiji Nakai , Naoki Okada , Tsunehiro Sato , Yoshiyuki Matsumoto , Masami Nakao , Masanori Sahara , Kouji Habu , Hiromu Sugano , Masaru Yamamoto , Tunehiro Mori
IPC分类号： F02D45/00 , F02B3/06 , F02D41/14 , F02D41/20 , F02D41/24 , F02D41/38 , F02D41/40
CPC分类号： F02D41/402 , F02B3/06 , F02D41/1498 , F02D41/20 , F02D41/2438 , F02D41/2441 , F02D41/2467 , F02D2200/1015 , Y02T10/44
摘要： A diesel engine control system and control method capable of conducting accurate fuel injection unaffected by variations in injector performance caused by differences among individual injectors or change with aging. The diesel engine control system includes an injector for directly injecting fuel into a combustion chamber of a diesel engine, injection quantity controller for controlling fuel injection quantity by varying a period of electric current supply to the injector, estimator for estimating that an electric current supply period when a prescribed (stable) combustion state is obtained is the current supply period for injecting the amount of fuel required for the prescribed combustion state, and control data correcting device for correcting control data of the injection quantity controller based on the estimated current supply period.
摘要翻译：一种柴油发动机控制系统和控制方法，其能够进行精确的燃料喷射，不受喷射器性能的变化的影响，由各个喷油器之间的差异引起，或随着老化而变化。柴油机控制系统包括用于将燃料直接喷射到柴油发动机的燃烧室中的喷射器，用于通过改变对喷射器的电流供应的时间来控制燃料喷射量的喷射量控制器，用于估计电流供应周期当获得规定的（稳定）燃烧状态时，是用于喷射规定燃烧状态所需的燃料量的电流供给期间，以及基于估计电力供给期间校正喷射量控制器的控制数据的控制数据校正装置。

2. 发明授权

US07071719B2 Semiconductor device 失效
公开(公告)号：US07071719B2
公开(公告)日：2006-07-04
申请号：US10353272
申请日：2003-01-28
申请人： Tsunehiro Sato , Kiyotaka Hayashi
发明人： Tsunehiro Sato , Kiyotaka Hayashi
IPC分类号： G01R31/02
CPC分类号： G11C29/1201 , G11C29/30 , G11C29/48 , G11C2029/3202 , H01L24/01
摘要： A semiconductor device includes at least three circuit substrates laid one upon another. The device further includes first circuit elements mounted, respectively, on at least two of the three circuit substrates. It also includes a second circuit element mounted on one of the three circuit substrates and configured to change connection between the first circuit elements.

3. 发明申请

US20110055645A1 SEMICONDUCTOR TEST METHOD, SEMICONDUCTOR TEST APPARATUS, AND COMPUTER READABLE MEDIUM 审中-公开
标题翻译：半导体测试方法，半导体测试仪器和计算机可读介质
公开(公告)号：US20110055645A1
公开(公告)日：2011-03-03
申请号：US12873631
申请日：2010-09-01
申请人： Atsushi INOUE , Tsunehiro Sato
发明人： Atsushi INOUE , Tsunehiro Sato
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G06F11/263 , G11C29/56 , G11C29/56012 , G11C2029/1806 , G11C2029/2602 , G11C2029/5602
摘要： A semiconductor test apparatus includes an inputting module, a monitor, a converter, a storage, and a tester. The inputting module inputs addresses for first test, in which the addresses of a plurality of semiconductor memories are arrayed in an arbitrary order. The monitor monitors test time of the first test on each semiconductor memory. The converter sorts the addresses of the semiconductor memories based on the test time in order to convert the address for the first test to addresses for a second test. The storage stores the addresses for the second test. The tester tests each semiconductor device based on the addresses for the second test stored in the storage.
摘要翻译：半导体测试装置包括输入模块，监视器，转换器，存储器和测试器。输入模块输入用于第一测试的地址，其中多个半导体存储器的地址以任意顺序排列。监视器监视每个半导体存储器上的第一次测试的测试时间。转换器根据测试时间对半导体存储器的地址进行排序，以将第一测试的地址转换为第二测试的地址。存储器存储第二次测试的地址。测试仪基于存储在存储器中的第二测试的地址测试每个半导体器件。

4. 发明授权

US5917833A Testing apparatus for semiconductor device 失效
标题翻译：半导体器件测试装置
公开(公告)号：US5917833A
公开(公告)日：1999-06-29
申请号：US988471
申请日：1997-12-10
申请人： Tsunehiro Sato
发明人： Tsunehiro Sato
IPC分类号： G01R31/28 , G01R31/3193 , G11C29/26 , G11C29/44 , G11C29/56 , G11C29/00 , G11C7/00
CPC分类号： G11C29/26 , G01R31/31935 , G11C29/56
摘要： A testing apparatus for semiconductor device capable of preventing reduction in the number of devices to be simultaneously measured is provided. Address of a measurement section of a semiconductor device to be measured, input data inputted to the measurement section and expected data to be outputted from the semiconductor device when the input data is inputted are generated by an ALPG. Output data actually outputted from the semiconductor device when the input data is inputted and expected data are compared with each other at a comparison unit. Comparison result is outputted as fail information. By a test pass control unit, there is generated test pass information for selecting fail information on the basis of divisional test information inputted in the case where the cycle time of test is faster than the cycle time of the fail information storage memory. Memory cell within the fail information storage memory is selected on the basis of address of the measurement section. Thus, fail information is written into the selected memory cell on the basis of test pass information by a fail information write control unit.
摘要翻译：提供一种能够防止同时测量的设备的数量减少的半导体器件的测试装置。通过ALPG生成要测量的半导体器件的测量部分的地址，输入到测量部分的输入数据和输入数据时从半导体器件输出的期望数据。当输入数据被输入时，实际从半导体器件输出的输出数据和预期数据在比较单元中相互比较。比较结果作为失败信息输出。通过测试通过控制单元，生成用于根据在测试的周期时间比故障信息存储存储器的周期时间快的情况下输入的分割测试信息来选择失败信息的测试通过信息。基于测量部分的地址选择故障信息存储存储器内的存储单元。因此，故障信息写入控制单元基于测试通过信息将故障信息写入所选存储单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式