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1. 发明申请

US20070269959A1 Method of aligning mask layers to buried features 审中-公开
标题翻译：将掩模层对准掩埋特征的方法
公开(公告)号：US20070269959A1
公开(公告)日：2007-11-22
申请号：US11434643
申请日：2006-05-16
申请人： John E. Freeman , Steven E. Staller , Troy A. Chase , William J. Baney
发明人： John E. Freeman , Steven E. Staller , Troy A. Chase , William J. Baney
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： B81C3/002 , B81C2201/019
摘要： A method for fabricating microchip devices is provided. The method includes the steps of providing a first planar substrate, locating at least one first alignment feature in the surface of the first planar substrate, and bonding a second substrate to the surface of the first planar substrate. The method further includes the step of aligning subsequent process operations performed on at least one of the first and second substrates to visible alignment features of the first substrate, wherein the visible alignment features are at least one of the first alignment feature and a visible feature that corresponds to the location of the first alignment feature.
摘要翻译：提供了一种用于制造微芯片器件的方法。该方法包括以下步骤：提供第一平面基板，将第一平面基板的表面中的至少一个第一对准特征定位，以及将第二基板接合到第一平面基板的表面。该方法还包括将在第一和第二基板中的至少一个执行的后续处理操作与第一基板的可见对准特征对准的步骤，其中可见对准特征是第一对准特征和可见特征中的至少一个，对应于第一对准特征的位置。

2. 发明授权

US06500348B2 Deep reactive ion etching process and microelectromechanical devices formed thereby 失效
标题翻译：深反应离子蚀刻工艺和由此形成的微电子机械装置
公开(公告)号：US06500348B2
公开(公告)日：2002-12-31
申请号：US09782394
申请日：2001-02-14
申请人： Troy A. Chase , John C. Christenson
发明人： Troy A. Chase , John C. Christenson
IPC分类号： H01L2100
CPC分类号： B81C1/00579 , B81C2201/0132 , G01P15/0802 , G01P15/0888 , G01P15/125
摘要： A process for forming a microelectromechanical system (MEMS) device by a deep reactive ion etching (DRIE) process during which a substrate overlying a cavity is etched to form trenches that breach the cavity to delineate suspended structures. In order to eliminate or at least reduce heat and/or charge accumulation that accelerates the DRIE etch rate of certain suspended structures, means are provided to electrically and/or thermally tie the suspended structures to each other and/or the surrounding bulk substrate. As a result, the process window is increased to allow slower-etching structures to be etched to completion without overetching the more rapidly-etched structures.
摘要翻译：用于通过深反应离子蚀刻（DRIE）工艺形成微机电系统（MEMS）器件的方法，在该方法中蚀刻覆盖空腔的衬底以形成破坏腔体以描绘悬浮结构的沟槽。为了消除或至少减少加速某些悬挂结构的DRIE蚀刻速率的热和/或电荷累积，提供了将悬浮结构电耦合和/或热连接到彼此和/或周围的体基底的装置。结果，增加了工艺窗口以允许将蚀刻蚀刻较慢的结构蚀刻成完成，而不会过蚀刻更快蚀刻的结构。

3. 发明授权

US07118991B2 Encapsulation wafer process 失效
标题翻译：封装晶圆工艺
公开(公告)号：US07118991B2
公开(公告)日：2006-10-10
申请号：US10708936
申请日：2004-04-01
申请人： Troy A. Chase , James H. Logsdon , James Kingery
发明人： Troy A. Chase , James H. Logsdon , James Kingery
IPC分类号： H01L21/30 , H01L21/46 , H01L21/302 , H01L21/461
CPC分类号： B81C1/00333 , B81C2203/0118
摘要： A method of processing a wafer, and particularly a cap wafer configured for mating with a device wafer in the production of a die package. Masking layers are deposited on oxide layers present on opposite surfaces of the wafer, after which the masking layers are etched to expose regions of the underlying oxide layers. Thereafter, an oxide mask is formed on the exposed regions of the oxide layers, but is prevented from forming on other regions of the oxide layers masked by the masking layers. The masking layers are then removed and the underlying regions of the oxide layers and the wafer are etched to simultaneously produce through-holes and recesses in the wafer. The oxide mask is then removed to allow mating of the cap wafer with a device wafer.
摘要翻译：一种处理晶片的方法，特别是在制造模具封装中配置成与器件晶片配合的盖晶片。掩蔽层沉积在存在于晶片的相对表面上的氧化物层上，之后蚀刻掩模层以暴露下面的氧化物层的区域。此后，在氧化物层的暴露区域上形成氧化物掩模，但是防止在被掩蔽层掩蔽的氧化物层的其它区域上形成氧化物掩模。然后去除掩模层，并蚀刻氧化物层和晶片的下面的区域，以同时在晶片中产生通孔和凹槽。然后去除氧化物掩模以允许盖晶片与器件晶片的匹配。

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